12 results about "Feed forward equalization" patented technology

Embodiments of the present application provide a parameter adjustment method, a communication device, and a storage medium. The method is applied to a first communication device having a first transmit link and a first receive link. The method comprises: acquiring a first transmit-end transfer function corresponding to the first transmit link (110); by means of the first receive link, receiving a first signal sent by a second communication device, the second communication device having a second receive link, and the first signal comprising a first receive-end transfer function corresponding to the second receive link (120); on the basis of the first transmit-end transfer function and the first receive-end transfer function, obtaining a first feed-forward equalization parameter corresponding to the first transmit link (130); and, on the basis of the first feed-forward equalization parameter, performing parameter adjustment on feed-forward equalization of the first transmit link (140).

A receiver includes a partial response (PR) system that receives a received signal from a transmitter over a channel and equalize the received signal such that there is a controlled relationship between consecutive values of equalized received symbols and transmitted data transmitted by the transmitter. The receiver also includes a decision feed forward equalization (DFFE) system that receives partial response signals from the PR system and cancel at least one of pre-cursor intersymbol interference (ISI) or post-cursor ISI introduced by the channel.

The application discloses a kind of underwater acoustic OFDM communication adaptive frequency domain equalization methods using Transform, it is related to underwater acoustic communication technical field, to solve the problems that existing underwater acoustic OFDM equalization method relies on cyclic prefix, is not sensitive to channel dynamic change, hard decision is prone to error propagation, the Transform framework containing only encoder is used in the present application, the soft decision of received symbol is completed by multi-head self-attention mechanism, and adaptive filtering is realized in combination with feedforward network;In the training phase, the loss function is calculated based on the network output and the true value, and the network parameters and the feedforward equalization filter coefficients are updated synchronously;In the inference phase, the network output is fed back to update the filter coefficients, and the real-time changes of the channel are adapted;The present application significantly reduces the probability of error propagation, and improves the communication reliability under complex underwater acoustic channel.

There is provided a system and a method for filtering out glitches in a SerDes transmitter. The SerDes transmitter includes a latency generation block, and a 2-to-1 serializer. The latency generation block is configured to synchronize a feed forward equalization (FFE) signal to a half rate domain by creating a latency in a FFE enable signal, and provide the synchronized FFE enable signal to a plurality of synchronized FFE selection multiplexers. The SerDes transmitter further includes a 2-to-1 serializer that is configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain.

The embodiment of the invention provides a parameter adjustment method, communication equipment and a storage medium, the method is applied to first communication equipment with a first transmitting link and a first receiving link, and the method comprises the following steps: acquiring a first transmitting end transfer function corresponding to the first transmitting link; a first signal sent by second communication equipment is received through the first receiving link, the second communication equipment is provided with a second receiving link, and the first signal comprises a first receiving end transfer function corresponding to the second receiving link; obtaining a first feed-forward equalization parameter corresponding to the first transmitting link according to the first transmitting end transfer function and the first receiving end transfer function; and performing parameter adjustment on feed-forward equalization of the first transmitting link according to the first feed-forward equalization parameter. In the whole parameter adjustment process, a manual parameter adjustment mode in related technologies does not need to be adopted, so that a large amount of time consumed by manual parameter adjustment can be saved, and the adjustment efficiency of the FFE parameters of the link can be effectively improved.

The application provides a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm, relates to the technical field of data transmission, and comprises the following steps: obtaining a first sequence obtained by performing digital-to-analog conversion and downsampling processing on a preset PRBS sequence and a second sequence obtained by performing alignment and downsampling processing on an expected sequence of the preset PRBS sequence; performing correlation operation on the first sequence and the second sequence to obtain a correlation operation result, and adjusting the second sequence to be aligned with the first sequence based on the correlation operation result; the correlation operation result comprises a correlation maximum value and a correlation minimum value for measuring the correlation degree; performing equalization processing on the first sequence by using an FFE algorithm to obtain an error sequence between the first sequence after equalization processing and the second sequence after alignment adjustment, performing bias error calibration and gain error calibration based on an expected value and a standard deviation of the error sequence; and performing time mismatch error calibration based on time errors of channels.

The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.

Embodiments included herein are directed towards a feed forward equalization (FFE) transmission circuit. The circuit may include a data serializer and data signal generator circuit and a most significant bit driver slice circuit configured to receive a first output from the data serializer and data signal generator circuit. The FFE transmission circuit may further include a least significant bit driver slice circuit configured to receive a second output from the data serializer and data signal generator circuit and a hybrid emphasis equalization slice circuit configured to receive a third output from the data serializer and data signal generator circuit.

Embodiments of the present disclosure provide systems and methods for implementing separate and orthogonal impedance tuning (Zcal) and feed forward equalization (FFE) operations of a segmented multiple level source-series terminated (SST) transmitter. An SST transmitter output driver comprising a plurality of parallel-connected output driver slices coupled to a data communication link and a multiple-tap FFE unit comprising at least one pre-cursor tap, main tap or post-cursor tap. The system performs impedance tuning within each of the plurality of parallel-connected output driver slices of the output driver. The system performs FFE resolution on the plurality of parallel-connected output driver slices of the output driver by assigning respective ones of the plurality of parallel-connected output driver slices to a specific FFE tap of the of the at least one pre-cursor tap, main tap or post-cursor tap of the FFE unit.

The application discloses a high-speed serial deserializing receiver based on a dual-MLSD architecture, on the basis of feedforward equalization, in order to cope with the different requirements of the number of MLSD states in the two scenarios that the correlation coefficient is less than or greater than the mode threshold, a dual-MLSD (Dual-MLSD) architecture containing an RS-MLSD with power consumption mode and an FS-MLSD with limit performance mode is designed, the high-speed serial state, the branch decoding process and the independent decoupling are designed into a 2-state 4-branch decoding module, and an Arburg estimation module is constructed to calculate the correlation coefficient value of the high-speed serial signal, that is, the value, the switching of the two modes is completed in cooperation with the low-state and post-filtering module and the high-state decoding module, the optimal area design is achieved, and the optimal power consumption is achieved in each scenario, and the MLSD decoder approximating the limit performance is achieved.

The invention provides a fractional feed-forward balanced transmitting circuit and a transmitter, in the fractional feed-forward balanced transmitting circuit, a line multiplexing module is used for outputting high-speed multiplexing data to a retimer; the retimer is used for delaying and outputting a time sequence high-speed signal to the feed-forward equalization module; the clock distribution circuit is used for outputting a delay control signal to the feed-forward equalization module; and the feed-forward equalization module is used for distributing the time sequence high-speed signal to a plurality of taps according to the control signal, performing fractional equalization on each tap according to the delay control signal, and synthesizing and outputting a full-rate data signal. According to the invention, the window time for acquiring the time sequence high-speed signal is distributed to each tap through the delay control signal output by the clock distribution circuit, so that each tap can freely slide back and forth, and fractional equalization is realized.

This invention discloses an output driving circuit disposed at the data transmitting end. A feedforward equalization module pre-emphasizes the data to be transmitted, thereby compensating for high-frequency components in the data and improving the output driving capability of the data transmitting end. An impedance matching unit then matches the output impedance of the output driving unit with the target output impedance to reduce signal reflection during the transmission of the pre-emphasized data to the data receiving end, further improving data transmission quality and efficiency. Therefore, this application uses a feedforward equalization module to compensate for high-frequency components in the data to be transmitted, improving the integrity and quality of the data during transmission in the channel. Furthermore, the impedance matching unit matches the output impedance of the output driving unit, reducing signal reflection of the pre-emphasized data and further improving the accuracy of the data received by the data receiving end.