The application discloses a high-speed serial deserializing
receiver based on a dual-MLSD architecture, on the basis of feedforward
equalization, in order to cope with the different requirements of the number of MLSD states in the two scenarios that the
correlation coefficient is less than or greater than the mode threshold, a dual-MLSD (Dual-MLSD) architecture containing an RS-MLSD with
power consumption mode and an FS-MLSD with limit performance mode is designed, the high-speed serial state, the
branch decoding process and the independent decoupling are designed into a 2-state 4-
branch decoding module, and an Arburg
estimation module is constructed to calculate the
correlation coefficient value of the high-speed serial
signal, that is, the value, the switching of the two
modes is completed in cooperation with the low-state and post-filtering module and the high-state decoding module, the optimal area design is achieved, and the optimal
power consumption is achieved in each
scenario, and the MLSD decoder approximating the limit performance is achieved.