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5 results about "Feed forward equalization" patented technology

The simplest approach is Feed Forward Equalization (FFE). This employs a finite impulse response filter (FIR) with a series of tap weights programmed to adjust the impulse and, by duality, frequency response (See Figure 3). This is the simplest implementation and can be designed entirely in the analogue domain.

Adaptive frequency domain equalization method for underwater acoustic OFDM communication using transformer

The application discloses a kind of underwater acoustic OFDM communication adaptive frequency domain equalization methods using Transform, it is related to underwater acoustic communication technical field, to solve the problems that existing underwater acoustic OFDM equalization method relies on cyclic prefix, is not sensitive to channel dynamic change, hard decision is prone to error propagation, the Transform framework containing only encoder is used in the present application, the soft decision of received symbol is completed by multi-head self-attention mechanism, and adaptive filtering is realized in combination with feedforward network;In the training phase, the loss function is calculated based on the network output and the true value, and the network parameters and the feedforward equalization filter coefficients are updated synchronously;In the inference phase, the network output is fed back to update the filter coefficients, and the real-time changes of the channel are adapted;The present application significantly reduces the probability of error propagation, and improves the communication reliability under complex underwater acoustic channel.
Owner:KUNMING UNIV OF SCI & TECH

A TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm

The application provides a TIADC channel mismatch calibration method and system based on a feedforward equalization algorithm, relates to the technical field of data transmission, and comprises the following steps: obtaining a first sequence obtained by performing digital-to-analog conversion and downsampling processing on a preset PRBS sequence and a second sequence obtained by performing alignment and downsampling processing on an expected sequence of the preset PRBS sequence; performing correlation operation on the first sequence and the second sequence to obtain a correlation operation result, and adjusting the second sequence to be aligned with the first sequence based on the correlation operation result; the correlation operation result comprises a correlation maximum value and a correlation minimum value for measuring the correlation degree; performing equalization processing on the first sequence by using an FFE algorithm to obtain an error sequence between the first sequence after equalization processing and the second sequence after alignment adjustment, performing bias error calibration and gain error calibration based on an expected value and a standard deviation of the error sequence; and performing time mismatch error calibration based on time errors of channels.
Owner:WUHAN MINGYANG TECH CO LTD

Hybrid-emphasis equalization circuit

Embodiments included herein are directed towards a feed forward equalization (FFE) transmission circuit. The circuit may include a data serializer and data signal generator circuit and a most significant bit driver slice circuit configured to receive a first output from the data serializer and data signal generator circuit. The FFE transmission circuit may further include a least significant bit driver slice circuit configured to receive a second output from the data serializer and data signal generator circuit and a hybrid emphasis equalization slice circuit configured to receive a third output from the data serializer and data signal generator circuit.
Owner:CADENCE DESIGN SYST INC

A high-speed serial deserializing receiver based on a double MLSD architecture

The application discloses a high-speed serial deserializing receiver based on a dual-MLSD architecture, on the basis of feedforward equalization, in order to cope with the different requirements of the number of MLSD states in the two scenarios that the correlation coefficient is less than or greater than the mode threshold, a dual-MLSD (Dual-MLSD) architecture containing an RS-MLSD with power consumption mode and an FS-MLSD with limit performance mode is designed, the high-speed serial state, the branch decoding process and the independent decoupling are designed into a 2-state 4-branch decoding module, and an Arburg estimation module is constructed to calculate the correlation coefficient value of the high-speed serial signal, that is, the value, the switching of the two modes is completed in cooperation with the low-state and post-filtering module and the high-state decoding module, the optimal area design is achieved, and the optimal power consumption is achieved in each scenario, and the MLSD decoder approximating the limit performance is achieved.
Owner:CHENGDU YONGZHI TECHNOLOGY CO LTD

An output driver circuit

This invention discloses an output driving circuit disposed at the data transmitting end. A feedforward equalization module pre-emphasizes the data to be transmitted, thereby compensating for high-frequency components in the data and improving the output driving capability of the data transmitting end. An impedance matching unit then matches the output impedance of the output driving unit with the target output impedance to reduce signal reflection during the transmission of the pre-emphasized data to the data receiving end, further improving data transmission quality and efficiency. Therefore, this application uses a feedforward equalization module to compensate for high-frequency components in the data to be transmitted, improving the integrity and quality of the data during transmission in the channel. Furthermore, the impedance matching unit matches the output impedance of the output driving unit, reducing signal reflection of the pre-emphasized data and further improving the accuracy of the data received by the data receiving end.
Owner:SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD