Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Groove insulated gate type source-leakage composite field plate transistor with high electron mobility

A technology with high electron mobility and insulated gate type, which is applied in the field of microelectronics, can solve the problems of reducing device yield, increasing device difficulty, and complicated manufacturing process, so as to improve breakdown voltage, reduce gate leakage current, and enhance reliability effect

Inactive Publication Date: 2009-04-22
XIDIAN UNIV
View PDF0 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the manufacturing process of the high electron mobility transistor using the stacked field plate structure is relatively complicated. Each additional layer of field plate requires additional process steps such as photolithography, metal deposition, insulating dielectric material deposition, stripping, and cleaning. To make the insulating dielectric material deposited under the field plates of each layer have an appropriate thickness, cumbersome process debugging must be carried out, thus greatly increasing the difficulty of device manufacturing and reducing the yield of devices

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Groove insulated gate type source-leakage composite field plate transistor with high electron mobility
  • Groove insulated gate type source-leakage composite field plate transistor with high electron mobility
  • Groove insulated gate type source-leakage composite field plate transistor with high electron mobility

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] The production substrate is sapphire, and the insulating dielectric layer is SiO 2 , the passivation layer is SiN, the protective layer is SiN, the source field plate, the drain field plate and each floating field plate are Ti / Au metal combination source-drain compound field plate high electron mobility transistor, and the process is:

[0062] 1. Using metal organic chemical vapor deposition technology to epitaxially undoped transition layer 2 with a thickness of 1 μm on the sapphire substrate 1, the transition layer is composed of AlN material with a thickness of 33 nm and GaN material with a thickness of 0.967 μm from bottom to top constitute. The process conditions used for the epitaxial lower layer AlN material are: temperature 590°C, pressure 160 Torr, hydrogen gas flow rate 4700 sccm, ammonia gas flow rate 4700 sccm, aluminum source flow rate 35 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1050°C, pressure 160 Torr,...

Embodiment 2

[0072] The production substrate is silicon carbide, the insulating dielectric layer is SiN, and the passivation layer is SiO 2 , the protective layer is SiO 2 , the source field plate, the drain field plate and each floating field plate are Ni / Au metal combination source-drain compound field plate high electron mobility transistor, the process is:

[0073] 1. An undoped transition layer 2 with a thickness of 2.1 μm is epitaxially formed on a silicon carbide substrate 1 by metal-organic chemical vapor deposition technology. Made of GaN material. The process conditions used for the epitaxial lower layer AlN material are: temperature 1020°C, pressure 165 Torr, hydrogen gas flow rate 4800 sccm, ammonia gas flow rate 4800 sccm, aluminum source flow rate 12 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1020°C, pressure 165 Torr, hydrogen flow rate 4800 sccm, ammonia gas flow rate 4800 sccm, gallium source flow rate 160 μmol / min.

[0...

Embodiment 3

[0083] The production substrate is silicon, and the insulating dielectric layer is Al 2 o 3 , the passivation layer is SiN, the protective layer is SiN, the source field plate, the drain field plate and each floating field plate are Pt / Au metal combined source-drain compound field plate high electron mobility transistors, and the process is:

[0084] 1. Using metal organic chemical vapor deposition technology to epitaxially undoped transition layer 2 with a thickness of 5 μm on the silicon substrate 1, the transition layer is composed of AlN material with a thickness of 125 nm and GaN material with a thickness of 4.875 μm from bottom to top constitute. The process conditions used for the epitaxial lower layer AlN material are: temperature 860°C, pressure 170 Torr, hydrogen gas flow rate 4900 sccm, ammonia gas flow rate 4900 sccm, aluminum source flow rate 35 μmol / min; the process conditions for the epitaxial upper layer GaN material are: temperature 1050°C, pressure 170 Torr...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a groove-insulated gate type source-drain composite field plate transistor with high electron mobility. The transistor comprises, from bottom to top, a substrate (1), a transition layer (2), a barrier layer (3), a source electrode (4), a drain electrode (5), an insulation medium layer (7), an insulated groove gate (8), a passivation layer (9), a source field plate (10), a drain field plate (12) and a protection layer (13); the source field plate is electrically connected with source electrode, and the drain field plate is electrically connected with the drain electrode, wherein, a groove (6) is opened on the barrier layer; and n floating field plates (11) are deposited on the passivation layer arranged between the source field plate and the drain field plate. All the floating field plates have the same size and are mutually independent, and the floating field plates are equidistantly distributed between the source field plate and the drain field plate. The n floating field plates, the source field plate and the drain field plate are completed on the passivation layer by one-time process. The transistor has the advantages of simple process, strong reliability and high output power, and can be used for fabricating power devices based on a wide band gap compound semiconductor material heterojunction.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to semiconductor devices, in particular to a grooved insulating gate type source-drain compound field plate high electron mobility transistor based on a wide bandgap compound semiconductor material heterojunction structure, which can be used as a basic device of a power system . technical background [0002] In today's world, power semiconductor devices such as power rectifiers and power switches have been widely used in many power fields such as switching power supplies, automotive electronics, industrial control, radio communications, and motor control. Power semiconductor devices must have the following two important parameters, namely high breakdown voltage and low on-resistance. The Baliga figure of merit reflects the compromise relationship between breakdown voltage and on-resistance in power semiconductor devices. In order to meet the needs of high breakdown voltage a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/78H01L29/778H01L29/06H01L21/336
Inventor 毛维杨翠郝跃过润秋
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products