Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table

A manufacturing method and uniaxial strain technology, applied in the field of microelectronics, can solve the problems of silicon wafers being easily broken, complicated process steps, and long manufacturing cycle, and achieve small surface roughness, simple manufacturing process, and low manufacturing cost. Effect

Inactive Publication Date: 2012-04-04
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The main disadvantages of this technology are: 1) the process steps are complex: the method must undergo thermal oxidation, H + Ion implantation, stripping annealing and other essential processes and related steps
3) Long production cycle: additional thermal oxidation, H + Process s

Method used

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  • Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table
  • Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table
  • Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] Embodiment 1: Preparation of 3-inch uniaxially strained GeOI wafer

[0037] 1. GeOI wafer selection: 3-inch (100) or (110) wafer ((100) or (110) refers to a certain crystal surface of the GeOI wafer crystal surface), Si substrate thickness 0.4mm, SiO 2 The buried insulating layer is 500nm thick, and the top Ge layer is 500nm thick.

[0038] GeOI wafer diameter selection: the larger the diameter of the GeOI wafer, the smaller the minimum bending radius of the bend, the greater the strain of the obtained uniaxially strained GeOI wafer, and the final electron migration of the uniaxially strained GeOI wafer The enhancement of rate and hole mobility is also higher. For the SiO-based 2 For uniaxially strained GeOI wafers with buried insulating layers, GeOI wafers with different diameters from 3 inches to 8 inches can be selected according to the different processes of GeOI devices and circuits.

[0039] GeOI wafer crystal face and crystal orientation selection: for the te...

Embodiment 2

[0057] Embodiment 2: Preparation of 4-inch uniaxially strained GeOI wafer

[0058] 1. GeOI wafer selection: 4-inch (100) or (110) crystal plane, Si substrate thickness 0.55mm, SiO 2 The buried insulating layer is 300nm thick, and the top Ge layer is 50nm thick.

[0059] 2. Selection of bending radius of curvature: According to the selected GeOI wafer, the radius of curvature of the bending table is selected to be 0.75m.

[0060] 3. GeOI wafer bending process steps:

[0061] 1) Place the Ge layer on the top layer of the GeOI wafer upwards (or downwards) on a clean stainless steel arc-shaped bending table, and its or direction is parallel to the bending direction, such as image 3 or Figure 4 shown;

[0062] 2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the GeOI wafer, 1 cm away from its edge;

[0063] 3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the GeOI wafer firs...

Embodiment 3

[0072] Embodiment 3: Preparation of 6-inch uniaxially strained GeOI wafer

[0073] 1. GeOI wafer selection: 6-inch (100) or (110) crystal plane, Si substrate thickness 0.68mm, SiO2 buried insulating layer thickness 1000nm, top Ge layer thickness 1000nm.

[0074] 2. Selection of bending radius of curvature: According to the selected GeOI wafer, the radius of curvature of the bending table is selected to be 0.5m.

[0075] 3. GeOI wafer bending process steps:

[0076] 1) Place the Ge layer on the top layer of the GeOI wafer upwards (or downwards) on an arc-shaped bending table, and its bending direction is parallel to the or direction, such as image 3 or Figure 4 shown;

[0077] 2) Two cylindrical horizontal pressure bars on the bending table are placed horizontally at both ends of the GeOI wafer, 1 cm away from its edge;

[0078] 3) Rotate the ejector nut of one of the pressure rods on the bending table to fix one end of the GeOI wafer first;

[0079] 4) Slowly turn the...

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Abstract

The invention discloses a manufacturing method of a single-shaft strain GeOI wafer based on a mechanical bending table, which comprises the following steps of: firstly, placing a Ge layer surface on the top layer of the GeOI wafer on the arc-shaped bending table downwards or upwards; secondly, respectively and horizontally placing two cylindrical stainless steel pressing rods at the two ends of the GeOI wafer which is 1cm away from the edge of the GeOI wafer; thirdly, slowly rotating nuts of the connected pressing rods, so that the GeOI wafer gradually bends along an arc-shaped tabletop till to be completely fitted with the arc-shaped tabletop; fourthly, placing the arc-shaped bending table carried with the GeOI wafer into an annealing furnace for annealing; fifthly, slowly cooling to the room temperature after the completion of the annealing and taking out the arc-shaped bending table carried with the GeOI wafer; and sixthly, rotating the nuts of the connected pressing rods and slowly lifting the pressing rods till the bent GeOI wafer restores the original shape. The invention has the following advantages that firstly, the raw materials are easy to obtain; secondly, the manufacturing cost is low; thirdly, the manufacturing process is simple; fourthly, the process temperature range is wide; fifthly, the yield rate is high; sixthly, the surface roughness is small; seventhly, the strain effect is good; and eighthly, the thermal property is good.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a semiconductor material manufacturing technology. Specifically, it is a new method for manufacturing uniaxially strained GeOI (Germanium On Insulator, germanium on buried insulating layer) wafers, which can significantly enhance the electron mobility and hole mobility of GeOI wafers, and improve the integration of GeOI devices and integration. The electrical and optical properties of the circuit. Background technique [0002] The electron and hole mobility of the semiconductor Ge are 2.8 times and 4.2 times that of Si, respectively, and its hole mobility is the highest among all semiconductors. Similar to strained Si, the carrier mobility of strained Ge is also greatly improved, and the hole mobility of buried channel strained Ge can be increased by 6-8 times. Therefore, Ge and strained Ge will be the best channel materials for Si-based CMOS devices and integrated circui...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L21/18
Inventor 王琳戴显英张鹤鸣董洁琼文耀民查冬宁静郝跃
Owner XIDIAN UNIV
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