Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor

Abstract

The invention discloses a manufacture method of a stacked gate SiC-metal insulator semiconductor (MIS) capacitor and mainly solves the problem of overlarge gate leakage current, too high SiC and SiO2 interface state density and poor breakdown characteristics of a SiC power MIS device. In the manufacture process, the standard wet process cleaning is carried out on an N type SiC epitaxial wafer; a layer of SiO2 film grows by a dry-oxygen oxidation method, and bottom layer gate media are formed; the grown SiO2 film is subjected to plasma treatment in an electron cyclotron resonance plasma enhanced-metal organic chemical vapor deposition (ECR PE-MOCVD) system; an atom layer deposition (ALD) method is used for depositing Al2O3 medium films, and top layer gate media are formed; substrate metals are evaporated by electron beams to form a zero electrode; and finally, the gate metal is formed through peeling, and the device manufacture is completed. The gate medium reliability of the SiC-MIS capacitor during the high-temperature and high-power application is improved, and the manufacture method can be used for the manufacture of large-scale SiC-MIS devices and circuits.

Description

Technical field: [0001] The invention belongs to the field of microelectronics technology, and relates to the manufacture of semiconductor devices, in particular to a method for manufacturing a stacked gate SiC-MIS capacitor to improve the breakdown characteristics of the device under acceptable interface state density conditions, so as to improve its high temperature , Reliability in high-power applications. Background technique: [0002] SiC has unique physical, chemical and electrical properties, and is a semiconductor material with great development potential in extreme applications such as high temperature, high frequency, high power and radiation resistance. The optimal working state of SiC power MOSFET is closely related to the interface characteristics and body characteristics of the gate dielectric insulating layer. SiO 2 The high interface state at the interface with SiC leads to low channel mobility, slow switching speed, affects device mobility, and increases l...

AI Technical Summary

Problems solved by technology

SiO 2 The high interface state at the interface with SiC leads to low channel mobility, slow switching speed, affects device mobility, and increases leakage current, resulting in an increase in threshold voltage and low-frequency 1 / f noise. Currently, high-reliability SiC- There are the following problems in MOS capacitors: SiC-MOS capacitors made by thermal oxidation have a high interface state density. In addition, under high field stress, the F-N current in the oxide layer on SiC will become very large, especially at high temperatures. Hot SiO during operation 2 There is an increase in leakage current and EBD drift in the dielectric breakdown electric field, which accelerates the failure of the oxide layer. From this we can see that the thermal oxidation method is not an ideal gate dielectric technology

[0003] In order to improve the properties of the SiC-MOS capacitor interface and improve the reliability of the gate dielectric, the current main methods focus on the research of the annealing process, such as the traditional Ar, H 2 Annealing, nitrogen oxide annealing (NO, N 2 O), N ion implantation before oxidation, and these are the principles of introducing more Ar, H and N elements at the interface to reduce the interface state density, but it is found through experiments that the proportion of elements introduced by these methods is very small, and the interface The density of states cannot be reduced very well; in addition, some high-K materials such as Gd are used to improve the reliability of the gate dielectric 2 o 3 , HfO 2 , AlN, Si 3 N 4 etc. as gate dielectrics, but studies have shown that there is still a high gate leakage current in SiC-MIS capacitors made of these gate dielectric materials

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