2 results about "MIS capacitor" patented technology

This application belongs to the field of semiconductor technology and provides a high-voltage LDMOS device and its fabrication method. The high-voltage LDMOS device includes: a semiconductor substrate, a buried oxide region, a P-type well region, a source region, a P-type base region, a drain region, a drift region, a passivation layer, a dielectric layer, a source electrode, a drain electrode, a gate electrode, and a metal field plate. The dielectric layer is used to connect the drain electrode and the semiconductor substrate. By adding the dielectric layer, a MIS capacitor can be formed, making the electric field distribution near the drain region more uniform, thereby optimizing the electric field in the drain region, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage in existing devices. By setting the metal field plate, the breakdown voltage space of the drain region can be fully utilized, and the electric field near the drain region can be introduced into the device, reducing the electric field pressure near the drain region, improving the breakdown voltage of the device, and thus improving the breakdown voltage capability of the device.

A combined metal-oxide-semiconductor (MOS) and metal-insulator- semiconductor (MIS) capacitor assembly, and a method of forming thereof, is provided. The method of forming the capacitor assembly includes steps of forming an oxide layer on a surface of a substrate comprising a semiconductor material; forming an insulator layer over at least a portion of the oxide layer; depositing a first conductive layer over at least a portion of the oxide layer; depositing a second conductive layer over at least a portion of the insulator layer; depositing a first terminal on the first conductive layer; and depositing a second terminal on the second conductive layer.