Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

The invention relates to a semiconductor device and a manufacturing method therefor, and an electronic apparatus. The manufacturing method comprises the steps of providing a semiconductor substrate with a PMOS region and an NMOS region, wherein the PMOS region comprises a first dummy gate electrode, and the NMOS region comprises a second dummy gate electrode; also forming an interlayer dielectric layer on the semiconductor substrate; forming an SiO<2> layer on the semiconductor substrate through deposition; removing the first dummy gate electrode to form a trench; forming a work function metal layer in the trench and on the SiO<2> layer through deposition; executing a planarization process; forming a patterned hard mask layer on the semiconductor substrate; etching and removing the second dummy gate electrode according to the patterned hard mask layer, wherein the etching comprises main etching and terminal point etching; etching gas adopted in the etching comprises NF<3> and H<2>; and executing an etching post-processing process. By adoption of the manufacturing method, damage and agglomeration defects of the interlayer dielectric layer are avoided, thereby improving the consistency of the device, ensuring the stability of the device, and finally improving the performance and the yield of the device.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the rapid development of microelectronics technology, the core of microelectronics technology - Complementary Metal Oxide Semiconductor (CMOS) technology has become the supporting technology of modern electronic products. In the semiconductor manufacturing process, various materials can be used as the gate electrode and gate dielectric of CMOS devices. Traditional CMOS devices usually use silicon oxynitride (SiON) as the gate dielectric layer, and doped Doped polysilicon is used as the gate electrode material. However, with the continuous improvement of integrated circuit manufacturing technology, the continuous improvement of chip integration, the reduction of technology nodes, and the trend of size change, more and more ad...

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Problems solved by technology

There are many problems in the process of removing the dummy gate at present: 1) the introduction of the interface layer and / or the etching process will produce a TiN (titanium nitride) interface layer, and the TiN interface layer will increase the threshold voltage of the device. However, the TiN interface layer The damage of the device will cause problems such as high leakage, diffusion of the metal aluminum layer, and failure of time-dependent dielectric breakdown (Time dependent dielectric breakdown, TDDB) performance; 2) dry etching and wet etching will consume interlayer Dielectric layer, wherein, the consumption of a large number of interlayer dielectric layers will lead to metal residues and lower gate height, thereby reducing the power of the device, and finally seriously affecting the yield of the device; 3) because the main etching process has a long The process time and the use of HBr gas will randomly generate condensation defects in the metal gate area, which will affect the filling of the work function metal layer and the metal layer gate and form holes in the metal gate, reducing the yield of the device; 4) The chemicals used in the post-etch process of forming NMOS metal gates by wet etching process are difficult to remove a large amount of polymer

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