Epitaxial wafer manufacturing method and epitaxial wafer

A manufacturing method and wafer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as the occurrence of particles, the reduction of oxygen precipitates, and the increase of workload.
CN108511317BActive Publication Date: 2021-10-22SUMCO CORP

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SUMCO CORP
Publication Date
2021-10-22

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Abstract

The invention provides a method that can exert the gettering ability brought by crystal defects and has a defect density of 10 on the surface of the epitaxial layer. 2 piece / cm 2 The following epitaxial wafer manufacturing method. The manufacturing method of this epitaxial wafer is characterized in that it includes: a single crystal silicon growth step, and grows a doped silicon crystal by the Czochralski single crystal pulling method 11 atoms / cm 3 ~4.5×10 15 atoms / cm 3 single crystal silicon of nitrogen; a single crystal silicon cutting process, cutting out a silicon wafer from the single crystal silicon; and an epitaxial layer forming process, using the above silicon wafer as a substrate, and forming a single crystal silicon on the substrate by vapor phase growth The epitaxial layer is an epitaxial layer, and the epitaxial layer is formed at a temperature ranging from 1050° C. to 1200° C. in the step of forming the epitaxial layer.
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Description

technical field

[0001] The invention of the present application relates to a method for manufacturing a high-quality wafer with a low surface defect density, that is, an epitaxial wafer, and the epitaxial wafer. Background technique

[0002] With the popularization of portable communication terminals including smart phones, the integration and high density of integrated circuit components (power devices) of silicon semiconductors is increasing year by year, and the quality requirements for silicon wafers forming power devices are becoming more and more stringent. . That is, as circuits become thinner with higher integration densities, in the so-called power device active regions where power devices are formed using wafers, changes that cause increases in leakage current and shorten the lifetime of carriers are more strictly restricted than before. Impurities such as crystal defects and metal-based elements other than dopants.

[0003] Conventionally, a substrate (wafer) cu...

Claims

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