Epitaxial wafer manufacturing method and epitaxial wafer

Abstract

The invention provides a method that can exert the gettering ability brought by crystal defects and has a defect density of 10 on the surface of the epitaxial layer. 2 piece / cm 2 The following epitaxial wafer manufacturing method. The manufacturing method of this epitaxial wafer is characterized in that it includes: a single crystal silicon growth step, and grows a doped silicon crystal by the Czochralski single crystal pulling method 11 atoms / cm 3 ~4.5×10 15 atoms / cm 3 single crystal silicon of nitrogen; a single crystal silicon cutting process, cutting out a silicon wafer from the single crystal silicon; and an epitaxial layer forming process, using the above silicon wafer as a substrate, and forming a single crystal silicon on the substrate by vapor phase growth The epitaxial layer is an epitaxial layer, and the epitaxial layer is formed at a temperature ranging from 1050° C. to 1200° C. in the step of forming the epitaxial layer.

Description

technical field [0001] The invention of the present application relates to a method for manufacturing a high-quality wafer with a low surface defect density, that is, an epitaxial wafer, and the epitaxial wafer. Background technique [0002] With the popularization of portable communication terminals including smart phones, the integration and high density of integrated circuit components (power devices) of silicon semiconductors is increasing year by year, and the quality requirements for silicon wafers forming power devices are becoming more and more stringent. . That is, as circuits become thinner with higher integration densities, in the so-called power device active regions where power devices are formed using wafers, changes that cause increases in leakage current and shorten the lifetime of carriers are more strictly restricted than before. Impurities such as crystal defects and metal-based elements other than dopants. [0003] Conventionally, a substrate (wafer) cu...

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Problems solved by technology

[0007] However, in the case of external gettering, there are problems such as an increase in cost due to an increase in the number of steps, and appearance of particles from the portion where distortion is applied, warping of the wafer due to processing, etc.

Intrinsic gettering, on the other hand, requires the presence of some degree of oxygen, but this may create defects that are detrimental to the formation of power devices

In addition, heat treatment is required to effectively make the groove, which also increases the workload

In addition, in the case of an epitaxial wafer, in the process of forming the epitaxial layer, it becomes a high temperature of 1050 to 1200°C, so the oxygen precipitates that should have become nuclei of micro defects in the wafer substrate will shrink and disappear, making it difficult to Grooves are formed in the subsequent heat treatment

Therefore, existing methods for intrinsic gettering cannot be effectively utilized

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