A perovskite/crystalline silicon stacked solar cell structure
A perovskite cell and stacked solar technology, applied in the field of solar cells, can solve problems such as inability to connect current directly, difficulty in application, complex laser opening technology, etc., and achieve the effects of uniform deposition, improved efficiency, and simple process
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Embodiment 1
[0026] The perovskite / crystalline silicon tandem solar cell structure includes: a bottom cell and a perovskite top cell; the bottom cell is a crystalline silicon-PERC bottom cell; the perovskite top cell includes a perovskite cell current-carrying cell The sub-transport layer A8, the perovskite absorption layer 9, the perovskite battery carrier transport layer B10, the transparent conductive film 11 and the top electrode grid line 12; the top electrode grid line 12 is located on the top of the transparent conductive film 11;
[0027] The structure of the crystalline silicon-PERC bottom cell from bottom to top is back electrode gate line 1, passivation layer A2, passivation layer B3, p-type silicon wafer 13, n-type doped emitter 14, ultra-thin The tunneling dielectric layer 6 and the heavily doped polysilicide film 7; the back electrode gate line 1 is embedded in the passivation layer A2 and the passivation layer B3 and the bottom is in contact with the p-type silicon wafer 13; ...
Embodiment 2
[0032] The perovskite / crystalline silicon tandem solar cell structure includes: a bottom cell and a perovskite top cell; the bottom cell is a crystalline silicon type-PERT bottom cell; the perovskite top cell includes a perovskite cell current-carrying cell The sub-transport layer A8, the perovskite absorption layer 9, the perovskite battery carrier transport layer B10, the transparent conductive film 11 and the top electrode grid line 12; the top electrode grid line 12 is located on the top of the transparent conductive film 11;
[0033] The structure of the crystalline silicon-PERT bottom cell from bottom to top is back electrode gate line 1, passivation layer A2, passivation layer B3, n-type silicon wafer 4, p-type doped emitter 5, ultra-thin The tunneling dielectric layer 6 and the heavily doped polysilicide film 7; the back electrode gate line 1 is embedded in the passivation layer A2 and the bottom of the passivation layer B3 in contact with the n-type silicon wafer 4; th...
Embodiment 3
[0039] The bottom cell is a planar n-PERT cell, the surface is prepared with silicon oxide, and the thickness of phosphorus-doped amorphous silicon is 20nm. After rapid annealing at 700°C for 10-300s, a tunnel junction is formed, and the contact resistivity is 10-20mΩ.cm2. The square resistance is 1000Ω / sq. On the tunnel junction, an electron transport layer with a thickness of 1-300 nm (which can be but not limited to TiO 2 , SnO 2 , ZnO, PCBM, C 60 , Nb 2 O 5 , SrTiO 3 , ICBA, ICTA and other materials), the thickness of 50 ~ 1500nm perovskite film (ABX 3 , where A is MA (methylamine), FA (formamidine), 5-AVA (5-ammonium isovalerate) or CS and their combination, B is Cu, Ni, Fe, Co, Mn, Cr, Cd, Sn , Pb, Pd, Ge, Eu or Yb and their combinations, X is I, Br or Cl and their combinations), a hole transport layer with a thickness of 1 to 300 nm (can be but not limited to spiro-OMeTAD, NiO x , CuI, CuSCN, NiO x , PEDOT: PSS, CuCSN, Graphene oxide, Cu 2 O, CuO, CuCaO 2 , P ...
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