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A method for fabricating vertical field-effect transistors with three-dimensional folded nanowire arrays

A vertical field effect and line array technology, applied in the field of microelectronics, can solve the problems of high manufacturing cost, difficulty in obtaining, and low yield, and achieve the effects of improving current load and driving capability, wide application value, and increasing integration density

Active Publication Date: 2022-04-22
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The nanowires prepared by the common vapor-liquid-solid (VLS) growth mode are mostly vertical random arrays, and it is difficult to directly realize reliable and low-cost positioning integration in the current planar electronic process.
Based on the top-down electron beam direct writing (EBL) technology to prepare transistor structures with nanowire diameters of 10-100 nanometers and channel lengths on the order of ten to hundreds of nanometers, the excellent characteristics of various new nanowire functional devices have been verified. , but due to factors such as high preparation cost and low yield, it is difficult to obtain large-scale and industrial applications
Through the bottom-up planar solid-liquid-solid (IP-SLS) nanowire growth catalyzed by nano-metal droplets, crystalline silicon, germanium and various alloy semiconductors with diameters below 100 nanometers can be prepared in large quantities by photolithography Nanowires can be used to prepare planar transistor arrays, but due to the limitations of the conventional photolithography process, the minimum channel length is relatively high, and it is impossible to prepare devices with shorter channels

Method used

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  • A method for fabricating vertical field-effect transistors with three-dimensional folded nanowire arrays
  • A method for fabricating vertical field-effect transistors with three-dimensional folded nanowire arrays
  • A method for fabricating vertical field-effect transistors with three-dimensional folded nanowire arrays

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Effect test

Embodiment 1

[0037] Such as figure 1 As shown, this embodiment provides a method for preparing a vertical gate transistor array by using a heterogeneous dielectric stack on a step to guide the growth of three-dimensional zigzag nanowires, which can be used to fabricate a vertical gate field effect transistor structure on a crystalline silicon substrate. The preparation process It can include the following steps:

[0038] 1) Using highly doped crystalline silicon as the substrate 1, using photolithography to define the position of the guide steps, and then etching the surface of the substrate by ICP etching. The etch process uses C 4 f 8 and SF 6 Gas mixing 3:4 deep silicon etching technology to obtain vertical three-dimensional steps, the height of the three-dimensional steps is 200nm; figure 1 as shown in a.

[0039] 2) Use plasma-enhanced PECVD to alternately deposit amorphous silicon nitride-silicon oxide-silicon nitride films, the thickness of each film is 40-60-40nm, and use ICP ...

Embodiment 2

[0047] This embodiment provides a method for growing single-layer three-dimensional zigzag nanowires guided by heterogeneous dielectric stacks on steps, such as figure 2 shown, including the following steps:

[0048] 1) Using etching technology to etch a single-layer three-dimensional step 5 shape on the patterned substrate;

[0049] 2) Deposit a homogeneous dielectric layer film on the substrate etched with three-dimensional steps, use photolithography to define the position and then etch to form a single-layer guide channel;

[0050] 3) preparing nanoscale catalytic metal particles 2 in the single-layer guide channel;

[0051] 4) Deposit a thin film layer covering the amorphous semiconductor precursor corresponding to the desired growth nanowire on the entire surface of the structure;

[0052] 5) Elevate the temperature so that the nano-scale catalytic metal particles change from solid to liquid in the single-layer guiding channel, the front end starts to absorb the amorp...

Embodiment 3

[0055] This embodiment provides a method for growing multi-layer three-dimensional zigzag nanowires guided by heterogeneous dielectric stacks on steps, such as image 3 shown, including the following steps:

[0056] 1) Using etching technology to etch a multi-layer three-dimensional step 4 shape on the patterned substrate;

[0057] 2) Deposit a heterogeneous dielectric layer film on a substrate etched with three-dimensional steps, use photolithography to define the position and then etch to form a multi-layer guide channel;

[0058] 3) preparing nanoscale catalytic metal particles 2 in the multilayer guide channel;

[0059] 4) Deposit a thin film layer covering the amorphous semiconductor precursor corresponding to the desired growth nanowire on the entire surface of the structure;

[0060] 5) Elevate the temperature to change the nano-scale catalytic metal particles from solid to liquid in the multi-layer guide channel, the front end starts to absorb the amorphous layer, an...

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Abstract

The invention discloses a method for preparing a vertical field effect transistor of a three-dimensional folded line nanowire array, comprising: 1) etching a three-dimensional step shape on a patterned substrate by using an etching technology; 2) etching a substrate with a three-dimensional step After depositing a dielectric film layer on top, etch again to expose the heterogeneous sidewalls near the three-dimensional steps, and then use selective etching to construct guide channels on the heterogeneous sidewalls; 3) Prepare nano 4) Deposit the amorphous semiconductor precursor thin film layer covering the entire surface of the structure corresponding to the desired growth nanowire; 5) Raise the temperature so that the nano-scale catalytic metal particles guide the channel from solid to liquid, and the front end The amorphous layer starts to be absorbed, and the zigzag crystalline nanowires are precipitated at the rear end; 6) The vertical part of the zigzag crystalline nanowires is used as the channel region, and the horizontal part is the source and drain electrode region to prepare a short-channel field-effect transistor.

Description

technical field [0001] The invention relates to a method for three-dimensional batch growth of nanowires, in particular to obtain sidewall channels by depositing heterogeneous stacks on steps for etching, and to grow three-dimensional zigzag nanowires in a planar solid-liquid-solid (IPSLS) manner The method of the array; belongs to the technical field of microelectronics. Background technique [0002] Junction-free transistors are key to developing a new generation of high-performance micro-nanoelectronics for applications such as logic, sensing, and display. The nanowires prepared by the current common gas-liquid-solid (VLS) growth mode are mostly vertical random arrays, and it is difficult to directly realize reliable and low-cost positioning integration in the current planar electronic process. Based on the top-down electron beam direct writing (EBL) technology to prepare transistor structures with nanowire diameters of 10-100 nanometers and channel lengths on the order ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/06H01L29/10H01L29/423
CPCH01L29/66666H01L29/0676H01L29/1037H01L29/401H01L29/42356
Inventor 余林蔚胡瑞金王军转
Owner NANJING UNIV
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