Sandwich accelerometer preparation method based on GIS cover plate

Abstract

The invention provides a sandwich accelerometer preparation method based on a GIS cover plate, the sandwich accelerometer comprises an upper cover plate, a lower cover plate and a middle layer sensitive structure, the upper cover plate comprises silicon-glass, the lower cover plate comprises silicon-glass, the method comprises the following steps: photoetching and corroding a plurality of unit patterns on silicon wafers of the upper and lower cover plates, and bonding with a glass sheet, the GIS structure is achieved through the procedures of backflow, grinding, polishing and the like; performing double-sided photoetching wet etching on the structural silicon wafer to form a structural pattern; and bonding the structural pattern in the structural silicon wafer and unit patterns corresponding to the structural pattern in the structural silicon wafer in the upper and lower cover plate silicon wafers in bonding equipment with set air pressure and set temperature. The method inherits the advantage of low stray capacitance of a classic silicon-glass-silicon-glass-silicon five-layer structure, meanwhile, surface electrode preparation is achieved, the sensitive chip with small stray capacitance and low stress is manufactured by using the SD-2 glass and Ti metal electrode with the coefficient of thermal expansion closer to that of silicon, and meanwhile, wafer-level batch performance testing is achieved.

Description

technical field [0001] The invention relates to the technical field of measurement and testing, in particular to a method for preparing a sandwich accelerometer based on a GIS cover plate. Background technique [0002] Based on the continuous development and advancement of MEMS technology, MEMS accelerometers have the advantages of small size, low power consumption, low cross-sensitivity, and mass production, and quickly occupy the fields of oil exploration, consumer electronics, aerospace, and automobile industries. General MEMS accelerometers are divided into capacitive, resonant, thermal convection, photoelectric and other detection principles. Among them, the capacitive detection principle has three structural forms: comb type, sandwich type and seesaw type, and comb type and seesaw type structure. Complicated and difficult to prepare; the sandwich structure is simpler and easier to prepare than the above two structures, and the overdamping control can be realized throug...

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Problems solved by technology

Among them, the silicon-silicon-silicon three-layer structure is represented by French Colibrys company. The silicon mass structure layer in the middle and the upper and lower silicon cover layers adopt hydrophilic bonding technology to achieve high-strength connection and hermetic packaging. In order to ensure interlayer insulation Silicon oxide is used as the dielectric layer. Usually, silicon oxide is prepared by thermal oxidation or chemical vapor deposition. The thickness of the oxide layer is usually within 5 μm, and its own dielectric constant is very large. Therefore, a large parasitic capacitance will be generated in the sealing ring area, usually parasitic The capacitance accounts for more than half of the basic capacitance of the sensitive chip, resulting in a large measurement system error, but this solution is easy to prepare electrodes on the surface of the wafer, which can realize batch screening tests at the wafer level; while silicon-glass-silicon-glass-silicon five The layer structure is represented by Murata Corporation of Japan. The silicon mass structure layer in the middle and the upper and lower cover layers adopt anodic bonding technology to achieve high-strength connection and hermetic packaging. The upper and lower cover plates are silicon-glass double-layer composite structures. The thickness of the connecting and sealing dielectric layer can usually reach more than 100 μm, so the parasitic capacitance in the sealing ring area is significantly reduced, but the sensitive chip electrodes based on this process plan are prepared on the side after the scribing is completed. This process has poor versatility and is sensitive. Chips cannot be batch screened and tested at the wafer level, reducing R&D and production efficiency

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