Semiconductor device

Abstract

There is disclosed a semiconductor device comprising a copper interconnect layer 7 where a copper film is buried in a concave in an insulating film 3 via a barrier metal film, wherein the copper interconnect layer 7 has a line / space ratio of 4.5 or less and an interconnect occupancy of 10 to 60%. It can effectively prevent dishing and erosion, as well as increase and dispersion in an interconnect resistance when forming damascene copper interconnects.

Description

[0001] 1. Field of the Invention[0002] This invention relates to a semiconductor device comprising copper interconnects and a manufacturing process therefor.[0003] 2. Description of the Prior Art[0004] Recent higher integration in a semiconductor device has increasingly required an interconnect layer having a lower resistance. Copper which is highly resistant to electromigration has been, therefore, widely used as an interconnect material. Copper as an interconnect material cannot be, however, anisotropically etched by RIE (Reactive Ion Etching), and thus is generally subject to a damascene process employing CMP (Chemical Mechanical Polishing). A conventional process for forming copper interconnects using CMP will be described with reference to FIG. 16.[0005] As illustrated in FIG. 16(a), on a silicon substrate 1 are sequentially formed a silicon nitride film 2 with a thickness of 100 nm and a silicon oxide film 3 with a thickness of 1000 nm. Then, in the silicon oxide film 3 are fo...

AI Technical Summary

Benefits of technology

[0023] Investigations for a semiconductor device have been conventionally conducted for improving an interconnect occupancy, aiming at a highly integrated device. On the contrary, in this invention, an interconnect occupancy is as low as 10 to 60%, which allows dishing and erosion to be effectively prevented when an interconnect layer is formed by a process employing CMP. A CMP process has a variety of advantages for forming copper interconnects because it can pattern copper, a less etchable material, by a relatively convenient procedure. The manufacturing process for a semiconductor device according to this invention can solve the problems of dishing and erosion in such a CMP process, leading to a high-quality and high-productivity process. The semiconductor device according to this invention has a particular structure wherein the interconnect occupancy is within the above range, so that dishing and erosion can be minimized when using a CMP process advantageous for forming copper interconnects, a resistance value can be stable, and a productivity can be satisfactory.

[0049] An interconnect layer in this invention has a configuration where copper interconnects are buried in a concave in an insulating film via a barrier metal film. The insulating film may be, in addition to a conventional silicon oxide film, a film made of a material with a lower dielectric constant for further accelerating a device, including organic films such as a benzocyclobutene (BCB) film, a parylene-N film and a CYTOP film; inorganic films such as a xerogel film and an HSQ (Hydrogen Silisesquioxane) film; and organic-inorganic composite films such as an HMO (Hydrogen peroxide (H.sub.2O.sub.2) / Methylsilane-based CVD) film. Among others, an HSQ film (k=2.8 to 3.2) exhibits stabler performance and is suitably used. As used herein, a barrier metal film is a film for preventing buried metal in a contact hole from being dispersed. The barrier metal film may be made of Ti, TiN, TiSiN, W, WN, WSiN, Ta, TaN or TaSiN. Preferable materials are Ta, TaN and TaSiN which can effectively prevent dispersion of copper. The barrier metal film consists of a single film or at least two films made of one or more of the above materials.

[0051] An interconnect occupancy as used herein is an area ratio of copper interconnects to the whole upper surface of the interconnect layer as defined above. For example, in FIG. 1(a) which is a plan view illustrating the upper surface of the interconnect layer in FIG. 1(b), an area ratio of the hatched area to the rectangle covering the whole surface is an interconnect occupancy. In this invention, the overall interconnect occupancy in the interconnect layer is preferably 60% or less, more preferably 50% or less, which may prevent dishing and erosion and can minimize increase and dispersion in an interconnect resistance. The lower limit for the interconnect occupancy is desirably 10% for avoiding extreme reduction in an interconnect density.

[0054] In this invention, when there is an interconnect area where a plurality of copper interconnects extend over 100 .mu.m or more in one direction (area (a)), it is desirable to set unique design criteria for the area. Specifically, a line / space ratio in copper interconnects in area (a) is preferably 4.5 or less, more preferably 4 or less, most preferably 3 or less. It may, as described later in Example 2, effectively prevent dishing and erosion and minimize increase and dispersion in an interconnect resistance. There are no restrictions for a lower limit for the line / space ratio, but it is preferably 0.5 or higher in the light of an interconnect density.

[0055] A plurality of interconnects with different line / space ratios may be formed in area (a). In such a case, more prominent effects may be achieved by controlling not only an average line / space ratio but also its distribution. Specifically, the line / space ratio may be up to 5 to more effectively minimize a dispersion in an interconnect resistance. As described later in Examples, a line / space ratio of more than 5 makes the dispersion in an interconnect resistance extremely higher. Thus, such interconnects may be eliminated to more effectively minimize a dispersion in the resistance.

[0063] Copper interconnects in this invention preferably have an average film thickness of 350 nm or less, more preferably 300 nm or less. There are no restrictions for its lower limit, but it may be, for example, 50 nm or more. It the film is too thick, a parasitic capacitance between adjacent interconnects may be increased, leading to crosstalk which make a high-speed operation difficult. FIG. 5 shows relationship between an interconnect thickness and an operation speed, where the abscissa and the ordinate indicate a loaded interconnect length and a circuit delay, respectively. A shorter circuit delay to the same interconnect length indicates a higher-speed operation. The thickness of the aluminum interconnects in this figure is 600 nm. Copper interconnects are used mainly for achieving a higher-speed operation than conventional aluminum interconnects. The figure indicates that it can be achieved with a thickness of 350 nm or less, desirably 300 nm or less. When a conventional process is used and a thickness is 350 nm or less, effects of reduction in a thickness due to dishing and erosion become much more prominent. As described above, this invention may be quite effective when applied to an interconnect structure comprising copper interconnects with a thickness of 350 nm or less, particularly 300 nm or less; specifically, thickness reduction can be effectively prevented while realizing a high-speed operation.

Problems solved by technology

Copper as an interconnect material cannot be, however, anisotropically etched by RIE (Reactive Ion Etching), and thus is generally subject to a damascene process employing CMP (Chemical Mechanical Polishing).

The above process of the prior art may, however, often cause dishing and / or erosion, resulting in a dispersed resistance as it increases.

In addition, it may cause electromigration, leading to a less reliable device.

Consequently, CMP may excessively proceed in the dense interconnect area, resulting in the surface concave as illustrated in FIG. 16(d).

Flatness may be more significantly degraded in a multilayer structure to cause significant problems such as short-circuit in interconnects and an increased interconnect resistance due to a reduced cross-section when forming damascene interconnects.

The periphery, therefore, tends to be excessively polished in relation to the inside.

In addition, there occurs uneven distribution of the polishing liquid between the periphery and the inside of the wafer surface.

It also contributes to excessive polishing of the periphery in comparison with the inside.

As described above, the wafer periphery is likely to be excessively polished in relation to the inside due to the process factors.

Furthermore, a difference in a film thickness becomes larger between copper interconnects, leading to a larger dispersion in an interconnect resistance.

In the process, dishing and erosion described above are technically significant problems.

However, none of these attempts have been adequately effective to prevent dishing or erosion.

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