Abrasive free formulations for chemical mechanical polishing of copper and associated materials and method of using same

a technology of chemical mechanical polishing and formulation, which is applied in the direction of basic electric elements, electrical equipment, water dispersions, etc., can solve the problems of incomplete etching, unsatisfactory surface polishing, and inability to achieve complete etching, etc., and achieves no surface defects, no dishing or oxide erosion, and good planarization efficiency

Inactive Publication Date: 2005-02-03
ADVANCED TECH MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0029] As will become apparent from the discussion that follows, the stable abrasive free formulation and method of using said formulation provide for removal of material and polishing of semiconductor ...

Problems solved by technology

If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems.
For example, when dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise.
Also, stringers or fences may arise from incomplete etching, polishing, or redeposition of metal.
If such selectivity is not maintained, unwanted dishing of copper and/or erosion of the dielectric material may occur.
This disparity in removal rates during the removal and polishing of the barrier material results in significant dishing of copper on the surface of the semiconductor wafer and/or poor removal of the barrier material.
Another problem with conventional CMP slurries is that the removal chemistry of the slurry is compositionally unstable.
Further, many of the colloidal and fumed abrasives agglomerate after relatively short time frames following addition to the supporting chemistry.
Both of these problems lead to significant operational obstacles such as the need for an expensive continuously recirculating distribution system equipped with filtration, chemistry monitoring, chemical addition equipment, and on-line particle monitors.
A further problem in commercial CMP slurries is that...

Method used

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  • Abrasive free formulations for chemical mechanical polishing of copper and associated materials and method of using same
  • Abrasive free formulations for chemical mechanical polishing of copper and associated materials and method of using same
  • Abrasive free formulations for chemical mechanical polishing of copper and associated materials and method of using same

Examples

Experimental program
Comparison scheme
Effect test

example 1

Polishing Performance Comparison of Abrasive Free Slurry Formulations (AFS) 1 and 2.

[0082] Table 2 provides a summary of the composition of two abrasive free slurries for polish performance comparison and Table 3 provides actual experimental results for the abrasive free polishing formulation as used on 8″ blanket films wafers of the following composition and thickness: copper wafer (5,000 Å thermal oxide, 300 Å tantalum, 1,500 Å PVD copper seed layer and 15,000 Å electroplated copper), tantalum nitride wafer (5,000 Å thermal oxide and 3,000 Å tantalum nitride), tantalum wafer (5,000 Å thermal oxide and 3,000 Å tantalum), and plasma enhanced tetraethyl orthosilicate (9,000 Å PETEOS).

TABLE 2Abrasive Free Slurry (AFS) Formulations AFS 1 and AFS 2AFS 1Final Weight AFS 2Final WeightComponentPercentComponentPercentHIO34.00HIO34.00IDA0.20IDA0.20H3PO40.75Citric Acid0.20KOH1.73KOH1.37H2OBalanceH2Obalance

[0083]

TABLE 3Polishing Performance Comparison AFS 1 vs. AFS 2AFS 1**AFS 2Room Temp.45...

example 2

Planarization Performance and Step Height Reduction

[0084] One object of CMP processing is to produce a uniform surface on the semiconductor wafer. The uniformity of the planarized surface is a function of several factors. FIGS. 5 and 7 are plots showing the step height remaining verses different copper / dielectric pattern densities on a Sematech 854 CMP AZ mask test wafer after underpolishing with an abrasive free polishing formulation for a bulk copper-polishing step according to one embodiment of the present invention. The initial step height before polishing was approximately 6000 Å. The data plotted in FIG. 5 is based on room temperature experimental conditions and the data plotted in FIG. 7, 45° C. The substantial step height reduction on the patterned wafers while underpolishing evidences the commercial viability of the present invention.

example 3

Planarization Performance and Array Recess

[0085]FIGS. 6 and 8 are plots showing the array recess verses different copper / dielectric pattern densities based on using the same abrasive free polishing formulation and substrate as in the previous step height reduction experimental. The data plotted in FIG. 6 is based on room temperature experimental conditions and the data plotted in FIG. 8, 45° C. The low levels of array recess are further evidence of the commercial viability of the abrasive free polishing formulation.

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Abstract

An abrasive free formulation for chemical mechanical polishing and method for using the formulation for polishing copper and related materials. The abrasive free formulation has a high removal rate on copper and a low removal rate on barrier material. The abrasive free formulation comprises at least an oxidizing agent and an activating agent.

Description

[0001] This application is a divisional of U.S. application Ser. No. 09 / 9535,805, filed on Aug. 23, 2001, now allowed.TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to the chemical mechanical polishing of semiconductor devices systems and methods, and more particularly, to a formulation and method for use in polishing metal films in semiconductor interconnection processes. BACKGROUND OF THE INVENTION [0003] The present invention relates to a polishing formulation for surfaces of a semiconductor wafer, and more particularly, to a polishing formulation and a method for using the polishing formulation to remove and polish metal containing materials layered on semiconductor wafer surfaces. [0004] Semiconductor wafers are used to form integrated circuits. The semiconductor wafer typically includes a substrate, such as silicon, upon which dielectric materials, barrier materials, and metal conductors and interconnects are layered. These different materials ...

Claims

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Application Information

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IPC IPC(8): C09G1/04C23F3/06H01L21/321
CPCC09G1/04H01L21/3212C23F3/06
Inventor MA, YINGJONES, MICHAELBAUM, THOMAS H.VERMA, DEEPAKBERNHARD, DAVID
Owner ADVANCED TECH MATERIALS INC
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