Method for manufacturing MIS (Metal-Insulator-Semiconductor) capacitor

Abstract

The invention provides a method for manufacturing an MIS (Metal-Insulator-Semiconductor) capacitor, which can effectively reduce the thickness of a film interface layer by etching a silicon island on an SOI (Silicon On Insulator) substrate and removing an oxide layer on the surface of the silicon island by adopting HF. The method comprises the following steps of: firstly, growing a thin oxynitride passivation layer on the Si surface by using a plasma atomic layer deposition method and adopting in-situ O2 and NH3 plasma so as to restrict the growth of the interface layer; and secondly, growing an HfLaO dielectric film by using a plasma growth manner, carrying out oxygen plasma aftertreatment on the HfLaO dielectric film in situ to reduce oxygen vacancy in the film; and thirdly, processing photoresist by using a chlorobenzene solution, so that burrs on the edge of the photoresist can be modified to ensure that the subsequent metal lifting process is simpler and more accurate. The MIS capacitor manufactured by adopting the method disclosed by the invention is beneficial to reduction of the quantity of additional interface layers, thinning of thickness of each interface layer, reduction of roughness of the interface layers, restriction of element dispersion between the substrate and the film and reduction of equivalent gate oxide thickness, and thus the electric property of the MIS capacitor is effectively improved.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and solid electronics, and in particular relates to a manufacturing method of an MIS capacitor. Background technique [0002] With the continuous development of large-scale integrated circuit technology, as the metal of the core device of silicon-based integrated circuits. The feature size of an oxide semiconductor field effect transistor (MOSFET) has been continuously shrinking in accordance with Moore's law. However, the thickness of the MOS tube gate dielectric is getting smaller and smaller, and it is close to its limit. When the thickness of the silicon dioxide gate dielectric is below 10nm (the processing limit of silicon material is generally considered to be 10nm line width), there will be problems such as increased tunneling current, pinhole defects, and poor reliability of performance failure. In order to solve these problems, some integrated circuit research and manufacturing...

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Problems solved by technology

[0006] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of manufacturing method of MIS electric capacity, for solving the additional interface layer that introduces in the MIS electric capacity preparation process in the prior art is too much and additional interface layer is too thick and Problems affecting its electrical performance

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