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SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device

An integrated device and inverted trapezoidal technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of limited electrical improvement effect of devices, small on-state current, high production cost, etc., to improve current drive and frequency characteristics, increased reliability, and improved processing capabilities

Inactive Publication Date: 2016-01-13
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, although the current switching ratio of the tunneling diode is high, the manufacturing cost is high and the on-state current is small; the graphene material carrier has a very high mobility, but the problem of too small a band gap has not been well solved.
FinFET devices can effectively reduce the leakage current, but the process is complicated and the effect of device electrical improvement is limited

Method used

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  • SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device
  • SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device
  • SOI-based CMOS integrated device with strain Ge channel and inverted trapezoidal grid and preparation method of integrated device

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Embodiment 1

[0029] please join figure 1 , figure 1 It is a flow chart of a preparation method of a SOI-based strained Ge channel inverted ladder gate CMOS integrated device according to an embodiment of the present invention, and the preparation method includes the following steps:

[0030] (a) select SOI substrate;

[0031] (b) forming a SiGe layer on the SOI substrate, growing a strained Ge layer and a Si cap layer on the SiGe layer to form an NMOS active region and a PMOS active region;

[0032] (c) forming an isolation trench by an etching process between the NMOS active region and the PMOS active region;

[0033] (d) Lithographically form an NMOS gate region pattern on the surface of the NMOS active region, and form a first double trapezoidal groove in the NMOS active region by using a particle beam etching process; form a PMOS gate region by photolithography on the surface of the PMOS active region Graphics, forming a second double trapezoidal groove in the PMOS active region by ...

Embodiment 2

[0078] See Figure 2a-Figure 2v , Figure 2a-Figure 2v It is a schematic diagram of a preparation method of a strained germanium (Ge) channel inverted ladder gate high-voltage CMOS according to an embodiment of the present invention. The ladder gate high-voltage CMOS integrated device is taken as an example to describe in detail, and the specific steps are as follows:

[0079] S101. Substrate selection. Such as Figure 2a As shown, the P-type doping is selected as 1×10 16 cm -3 ~3×10 16 cm -3 A silicon (Silicon-On-Insulator, SOI) substrate 201 on an insulating substrate with a top silicon (Si) thickness of 20-30 nm and an oxide layer thickness of 150-200 nm is the initial material.

[0080] S102 , growing an epitaxial layer. Such as Figure 2b As shown, a P-type silicon germanium (SiGe) epitaxial layer 202 with a thickness of 70-80 nm is grown on an SOI substrate by using the method of ultra-high vacuum chemical vapor deposition (UltrahighvacuumCVD, referred to as UHV...

Embodiment 3

[0128] See image 3 , image 3 It is a flow chart of another method for preparing a strained SiCMOS integrated device based on SOI double inverted ladder gate NMOS and PMOS according to an embodiment of the present invention. The strained SiCMOS device includes: an SOI substrate, silicon germanium ( SiGe) layer, strained germanium (Ge) layer, silicon (Si) cap layer, metal contact layer above the source and drain regions of NMOS devices and PMOS devices, and gate oxide formed by metal oxides below the gates of NMOS devices and PMOS devices layers, metal gates of NMOS and PMOS, and interconnection leads and passivation layers between separated NMOS and PMOS (not shown in the figure). Among them, the gates of the NMOS device and the PMOS device are as follows image 3 The process of the double inverted trapezoidal groove gate shown is prepared by the process method in the above-mentioned embodiment. Certainly, an isolation region between the NMOS and the PMOS is also included,...

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Abstract

The invention relates to an SOI-based CMOS integrated device with a strain Ge channel and an inverted trapezoidal grid and a preparation method of the integrated device. The preparation method comprises that an SOI substrate is selected; a SiGe layer is formed, and a strain Ge layer and a Si cap layer are grown to form NMOS and PMOS active regions; an isolated channel is formed by an etching technology; the surface of the NMOS active region is photo-etched to form an NMOS grid pattern, and a first double-trapezoid groove is formed by a particle beam etching technology; the surface of the PMOS active region is photo-etched to form a PMOS grid pattern, and a second double-trapezoid groove is formed by a particle beam etching technology; grid medium materials are formed at the surfaces of the NMOS and PMOS active regions respectively; the grid medium material at specific position of the surface of the PMOS active region is etched, and P type ions are injected to form a PMOS source-drain area, the grid medium material at specific position of the surface of the NMOS active region is etched, and N type ions are injected to form an NMOS source-drain area; NMOS and PMOS grids are formed; and metallization is carried out, the drain, source and grid leads are photo-etched to form the SOI-based CMOS integrated device with the strain Ge channel and inverted trapezoidal grid.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to an SOI-based strained Ge channel inverted ladder gate CMOS integrated device and a preparation method. Background technique [0002] Since the emergence of silicon integrated circuits in the 1960s, a general-purpose electronic circuit can be fabricated on a small single-crystal silicon wafer, realizing the miniaturization of electronic circuits; with the increase in demand for integrated circuits and research work With the deepening of the development, monolithic integrated systems and subsystems appeared, and gradually formed a sub-discipline of electronics that studies the formation of micro-miniature electronic circuits, systems and subsystems on solid (mainly semiconductor) materials, that is, microelectronics. Microelectronics is an emerging discipline developed on the basis of physics, electronics, material science, computer science, integrated c...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L27/092H01L29/10H01L29/423
CPCH01L21/823807H01L21/823828H01L21/823857H01L27/092H01L29/1054H01L29/42356
Inventor 刘翔宇苗渊浩胡辉勇张鹤鸣宋建军舒斌宣荣喜
Owner XIDIAN UNIV
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