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Gallium nitride device packaging structure

A device packaging and gallium nitride technology, which is applied in semiconductor devices, electrical solid state devices, semiconductor/solid state device components, etc., can solve problems such as the inability to effectively reduce the packaging area, increase the parasitic inductance of the device, and reduce the switching performance of the device

Active Publication Date: 2021-09-14
青岛聚能创芯微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existence of the DBC board not only increases the heat conduction path of the device, which in turn increases the thermal resistance of the device, but also increases the packaging cost
The cascode connection wire between Si MOSFET and GaN HEMT also increases the parasitic inductance of the device, which reduces the switching performance of the device
In addition, Si MOSFETs are arranged in parallel with GaN HEMTs, which cannot effectively reduce the packaging area

Method used

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  • Gallium nitride device packaging structure
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Effect test

Embodiment 1

[0082] Such as figure 1 As shown in FIG. 2 , it is a schematic top view of the GaN device packaging structure in the prior art. exist figure 1 Among them, a gallium nitride high electron mobility transistor chip 101 and a silicon metal oxide semiconductor field effect transistor chip 102 are packaged on the lead frame 100 respectively, and are connected by wires 103 . The gallium nitride high electron mobility transistor chip 101 and the silicon metal oxide semiconductor field effect transistor chip 102 are also respectively connected to the gate pin 100a, the source pin 100b and the drain of the lead frame 100 Pin 100c. In the above packaging structure, the two kinds of chips are respectively placed on the DBC board 104 . The existence of the DBC board 104 not only increases the thermal conduction path of the device, thereby increasing the thermal resistance of the device, but also increases the packaging cost. Due to the limited substrate area of ​​the lead frame 100, th...

Embodiment 2

[0092] The package form adopted by the gallium nitride device package structure provided by the present invention is not limited to the in-line TO package, but also includes SMD TO package, QFN package, DFN package, TOLL package, SOP package or SOIC package and other package forms. .

[0093] For example, if Figure 4 As shown, this embodiment also provides a GaN device packaging structure. Compared with the TO packaging structure provided in Embodiment 1, the difference of this embodiment is that the TOLL packaging form is adopted.

[0094] Specifically, such as Figure 4 As shown, in the GaN device packaging structure adopting the TOLL packaging structure, the first chip 301 and the second chip 302 are sequentially stacked on the lead frame 300 . Wherein, the first chip 301 includes a high voltage depletion gallium nitride high electron mobility transistor (GaN HEMT), and the second chip 302 includes a low voltage enhancement type silicon metal oxide semiconductor field ef...

Embodiment 3

[0100] Such as Figure 5 As shown, this embodiment provides a gallium nitride device packaging structure. Compared with the first embodiment, the difference of this embodiment is that a QFN packaging form is adopted.

[0101] Specifically, such as Figure 5As shown, in the GaN device package structure using the QFN package structure, the first chip 401 and the second chip 402 are sequentially stacked on the lead frame 400 . Wherein, the first chip 401 includes a high voltage depletion gallium nitride high electron mobility transistor (GaN HEMT), and the second chip 402 includes a low voltage enhancement type silicon metal oxide semiconductor field effect transistor (Si MOSFET). The gate 401a, source 401b and drain 401c of the gallium nitride high electron mobility transistor are located on the front side of the first chip 401; the gate 402a and source of the silicon-based metal oxide semiconductor field effect transistor 402b is located on the front side of the second chip 4...

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Abstract

The invention provides a gallium nitride device packaging structure. The gallium nitride device packaging structure comprises: a lead frame; a first chip packaged on the lead frame, wherein the first chip comprises a high-voltage depletion type gallium nitride high electron mobility transistor; and a second chip packaged on the first chip, and comprising a low-voltage enhanced silicon-based metal oxide semiconductor field effect transistor. By adopting a direct stacking mode, the drain electrode of the low-voltage enhancement type silicon-based metal oxide semiconductor field effect transistor is adhered to the source electrode of the high-voltage depletion type gallium nitride high electron mobility transistor chip by adopting the conductive film, so that binding wires in the packaging structure are reduced, and the parasitic inductance is reduced; the directly stacked structure also optimizes the layout of the chips, and effectively reduces the packaging area; and the packaging structure does not use a DBC board, so that the packaging cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a gallium nitride device packaging structure. Background technique [0002] The third-generation semiconductor material gallium nitride (GaN) has the advantages of large band gap, high electron mobility, and strong breakdown electric field. It can be used in high temperature, high voltage, and high frequency working environments, and has broad application prospects. The gallium nitride heterojunction structure has a strong two-dimensional electron gas, and it is a depletion device when no gate voltage is applied. Negative voltage is required to turn off the device, which brings inconvenience to the design of the driving circuit. Typically, a low-voltage enhancement-mode silicon-based metal-oxide-semiconductor field-effect transistor (SiMOSFET) and a high-voltage depletion-mode gallium nitride high electron mobility transistor (GaN HEMT) are cascoded s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/488
CPCH01L25/18H01L24/32H01L2224/32145H01L2224/48145H01L2224/48247H01L2224/0603
Inventor 窦娟娟李成袁理
Owner 青岛聚能创芯微电子有限公司
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