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Super junction IGBT device with low loss performance and production method thereof

A low-loss, device-based technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of weakening conductance modulation effect, large internal resistance of IGBT, weak overvoltage resistance, etc. Effects of extraction, reduced injection efficiency, and high blocking ability

Pending Publication Date: 2022-01-21
广州华浦电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, under high-voltage conditions, the IGBT has large internal resistance, large conduction loss, and weak overvoltage resistance. In addition, at the same level, the potential of the N-pillar region in the IGBT device is higher than that of the P-pillar region to form a reverse-biased PN junction , the lateral electric field pushes the holes into the P-pillar region and then flows into the source, causing the hole concentration to decrease, which will weaken the conductance modulation effect, thereby increasing the conductance power consumption

Method used

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  • Super junction IGBT device with low loss performance and production method thereof
  • Super junction IGBT device with low loss performance and production method thereof
  • Super junction IGBT device with low loss performance and production method thereof

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Embodiment 1

[0018] See figure 1 , figure 1 It is a schematic structural diagram of a super-junction IGBT device with low loss performance provided by an embodiment of the present invention. The device includes: collector (1), P collector region (2), N-buffer region (3), N- pillar region (4), P-pillar region (5), gate oxide layer (6), N-base region (7), P injection region (8), first gate (14), second gate (9 ), N+ implantation region (10), source metal (11), P+ implantation region (12) and P-base region (13).

[0019] The P-collector region (2) is located above the collector (1).

[0020] The N-buffer area (3) is located above the P collector area (2).

[0021] The N-pillar area (4) is located above the N-buffer area (3), and the right side of the N-pillar area (4) is provided with the P-pillar area (5); the P- The horizontal length of the pillar region (5) is half of the horizontal length of the N-pillar region (4).

[0022] The P-base region (13) is positioned above the N-pillar reg...

Embodiment 2

[0053] See Figure 2a-2h , Figure 2a-2h It is a schematic diagram of the manufacturing process of a super-junction IGBT device with low loss performance provided by the embodiment of the present invention. The preparation method of the super junction IGBT device with low loss performance comprises:

[0054] Step 1: The N doping is 3.7×10 15 cm -3 A groove with a depth of 50 μm and a width of 5.5 μm was etched on a silicon wafer.

[0055] see Figure 2a shown.

[0056] Step 2: Epitaxially grow P-type silicon in the etched groove as the P-pillar region, doped to 3.7×10 15 cm -3 .

[0057] see Figure 2b shown.

[0058] Step 3: Epitaxially grow a layer of P-type silicon on the silicon wafer with a thickness of 1.7 μm and a doping of 5.1×10 16 cm -3 ; and a layer of P-type silicon is grown on the P-type silicon with a thickness of 0.75 μm and a doping of 8.4×10 18 cm -3 .

[0059] see Figure 2c shown.

[0060] Step 4: Manufacturing a mask and then etching a groo...

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Abstract

The invention discloses a super junction IGBT device with low loss performance. The device comprises a collector electrode, a P collector electrode region, an N-buffer region, an N-pillar region, a P-pillar region, a gate oxide layer, an N-base region, a P injection region, a first grid electrode, a second grid electrode, an N + injection region, source electrode metal, a P + injection region and a P-base region. According to the invention, negative ions are injected into the oxide layer of the second grid electrode of the device, a depletion type P-channel MOS tube can be formed with a P-pillar region, an N-base region and a P injection region, the MOS tube can be used as a switch of a storage hole of the device, and when an IGBT is conducted, the MOS tube is closed and then stores the hole so that the conductivity modulation effect is improved, the on resistance of the device is reduced, and the conduction power consumption is decreased; and when the IGBT is closed, the MOS tube is opened to release holes, a low-resistance channel is provided, hole outflow is accelerated, the switching speed is increased, and the switching loss is reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a super-junction IGBT device with low loss performance and a preparation method thereof. Background technique [0002] IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) is currently the fastest growing hybrid power electronic device, which has the input of MOSFET (Metal Oxide Semiconductor FieldEffect Transistor, Metal Oxide Semiconductor Field Effect Transistor) It has the advantages of high impedance, low control power, simple drive circuit, high switching speed, and low switching loss. It also has the advantages of high current density, low saturation voltage, and strong current handling capability of bipolar power transistors. Three aspects are unmatched by other power devices. [0003] However, in the high-voltage state, the IGBT has large internal resistance, large conduction loss, and weak overvoltage resistance. In addition, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/08H01L29/10H01L29/423H01L29/739H01L21/28H01L21/331
CPCH01L29/7398H01L29/7397H01L29/66348H01L29/0684H01L29/401H01L29/42364H01L29/0821H01L29/1004H01L29/42356
Inventor 何艳静张飞翔江希袁嵩弓小武
Owner 广州华浦电子科技有限公司
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