Semiconductor flip-chip package and method for the fabrication thereof

Abstract

A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and precoated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder / flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction. With this configuration, the complaint solder / flexible encapsulant understructure absorbs the strain caused by the difference in the thermal coefficients of expansion between the chip and the substrate without bending the chip and substrate.

Description

[0001] This application claims the benefit of U.S. Provisional Application Nos. 60 / 053,407, filed Jul. 21, 1997, and 60 / 056,043, filed Sep. 2, 1997, and incorporates herein the disclosures of those applications in their entirety.[0002] The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of contract no. N00164-96-C-0089 awarded by Defense Advanced Research Projects Agency.FIELD OF THE INVENTION [0003] This invention relates generally to semiconductor chips electrically and mechanically connected to a substrate, particularly to flip-chip configurations. BACKGROUND OF THE INVENTION [0004] Flip-chip technology is well known in the art. A semiconductor chip having solder bumps formed on the active side of the semi-conductor chip is inverted and bonded to a substrate through the solder bumps by reflowing the solder. Structural solder joints are form...

AI Technical Summary

Benefits of technology

"The present invention provides a simple and cost-effective method for assembling a chip to a substrate by pre-coating the chip with underfilling encapsulant and pre-assembling it onto the substrate. The chip is then placed on the substrate and the solder bumps on the chip are reflowed while the encapsulant hardens, eliminating the need for labor-intensive underfill steps of the prior art. The invention also provides a method for avoiding gas bubbles or voids during assembly. The encapsulant consists of more than one layer, each layer performing different functions such as attachment, stress distribution, electrical redistribution, and reworkability. The bulk of the encapsulant is applied and partially or fully hardened prior to assembly on the substrate."

Problems solved by technology

One obstacle to flip-chip technology when applied to polymer printed circuits is the unacceptably poor reliability of the solder joints due to the mismatch of the coefficients of thermal expansion between the chip, having a coefficient of thermal expansion of about 3 ppm / ° C., and the polymer substrate, e.g. epoxy-glass having a coefficient of thermal expansion of about 16 to 26 ppm / ° C., which causes stress build up in the solder joints.

Because the structural solder joints are small, they are thus subject to failures.

The underfill process, however, makes the assembly of encapsulated flip-chip printed wire boards (PWB) a time consuming, labor intensive and expensive process with a number of uncertainties.

After reflow, due to the close proximity of the chip to the substrate, removing flux residues from under the chip is such a difficult operation that it is generally not done.

These residues are known to reduce the reliability and integrity of the encapsulant.

The reflowing of the solder bump and then underfilling and curing the encapsulant is a multi-step process that results in reduced production efficiency;

To underfill a flip-chip assembly takes too long because the material must flow through the tiny gap between the chip and the substrate;

The flux residues remaining in the gap reduce the adhesive and cohesive strengths of the underfill encapsulating adhesive, affecting the reliability of the assembly; and

As the size of chips increase, the limiting effect of capillary action becomes more critical and makes the encapsulation procedure more time consuming, more susceptible to void formation and to the separation of the polymer from the fillers during application.

This method suffers from the need to reserve an area in the center of the substrate that is free of circuitry in order to provide an unused space for the hole.

It also does not eliminate the problems of entrapped air bubbles.

The limitation of this technique is that in order for the molten solder to readily wet the substrate metallization and also to allow the solder, through surface tension, to self-align the chip bumps to the substrate metallization pattern, the material must maintain very low viscosity during the reflow step.

But the viscosity of these materials is severely increased by the presence of the required inorganic fillers.

As a result, this approach has failed to produce a material that can serve as both the flux and the encapsulant with the required low coefficient of thermal expansion and high modulus for optimum reliability.

Unfortunately, the effect of the encapsulant bending the substrate and the chip causes its own new set of problems.

One such problem is that the bending makes the chips susceptible to cracking.

Another such problem is that the degree of stress relief is highly dependent on the flexibility of the under-lying substrate and is thus an unpredictable function of the design of the printed circuit.

Another limitation is that relying on such bending for stress relief on the solder joints prevents the placement of flip chips directly opposite one another on a double-sided printed circuit.

Another limitation of prior art flip-chip attachment is the difficulty of performing rework.

Chip removal, once underfill has been performed, is very destructive to both the printed circuit board and the chip.

Rework is almost impossible with prior art materials and processes.

Another limitation of the prior art is the expense of applying solder bumps to a chip.

This method suffers from 1) long deposition times, 2) limitations on the compositions of solder that can be applied to those metals that can be readily evaporated, and 3) evaporating the metals over large areas where the solder is ultimately not wanted.

Also, since most solders contain lead, a toxic metal, evaporation involves removal and disposal of excess coated lead from equipment and masks.

Electroplating is a slow and expensive process that also deposits the solder over large areas where the solder is ultimately not wanted.

This technique is limited to bump dimensions that can be readily stencil printed, so it is not practical in bump pitches of 25 microns or less.

Another limitation of the prior art is the difficulty in distributing electrical signals from the small dimension of the chip to the large dimensions of the substrates.

Today, this discrepancy is bridged by creating expensive redistribution layers on the printed circuit.

Few manufacturers are able to produce printed circuits at the tight dimensional tolerances required for redistribution, but those who are capable of doing so achieve this with significant production yield penalties.

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