Semiconductor flip-chip package and method for the fabrication thereof

Abstract

A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and precoated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder / flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction. With this configuration, the complaint solder / flexible encapsulant understructure absorbs the strain caused by the difference in the thermal coefficients of expansion between the chip and the substrate without bending the chip and substrate.

Description

[0001] This application claims the benefit of U.S. Provisional Application Nos. 60 / 053,407, filed Jul. 21, 1997, and 60 / 056,043, filed Sep. 2, 1997, and incorporates herein the disclosures of those applications in their entirety.[0002] The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of contract no. N00164-96-C-0089 awarded by Defense Advanced Research Projects Agency.FIELD OF THE INVENTION [0003] This invention relates generally to semiconductor chips electrically and mechanically connected to a substrate, particularly to flip-chip configurations. BACKGROUND OF THE INVENTION [0004] Flip-chip technology is well known in the art. A semiconductor chip having solder bumps formed on the active side of the semi-conductor chip is inverted and bonded to a substrate through the solder bumps by reflowing the solder. Structural solder joints are form...

AI Technical Summary

Benefits of technology

[0025] In one aspect of the present invention, there is provided a first portion of an underfilling encapsulant and separate discrete solder bumps pre-coated and pre-assembled on a chip for assembly to a substrate. The first portion of encapsulant can be either a solid or a thick liquid, partially or fully uncured. A second portion of the encapsulant is applied to the substrate. The first portion of the encapsulant is filled, preferably highly filled, with a filler material to produce a reduced coefficient of thermal expansion and increased modulus. The second portion of the encapsulant is either lightly filled or completely devoid of filler material. At least the second portion of the encapsulant comprises an adhesive material with solder fluxing properties, for example, an adhesive flux. The first portion of the encapsulant can comprise a similar material or a conventional epoxy. The first portion is filled with a filler having a lower coefficient of thermal expansion and higher modulus than the encapsulant material without filler to increase the encapsulant's modulus and reduce its coefficient of thermal expansion. The invention provides a simple, cost-effective assembly procedure wherein the chip / first portion of encapsulant / discrete solder bump combination is placed on the substrate / second portion of encapsulant combination and subsequently heat is applied so that the solder is reflowed while simultaneously the encapsulant cures, without the labor intensive, time-consuming underfill steps of the prior art. Preferably, the second portion constitutes a relatively thin layer in the overall encapsulant structure which somewhat intermixes with the first portion during cure and has minimal effect on the reliability of the flip-chip structure, despite the second portion having generally a lower modulus and higher coefficient of thermal expansion than the first portion. An advantage of the present invention is that the lower viscosity of the unfilled or lightly filled second portion during the reflow process allows the solder to flow without impediment from the thick viscosity of the first portion of the encapsulant. The present invention provides a low coefficient of thermal expansion and high modulus in the first portion of the encapsulant while at the same time achieving good solder wetting and chip self aligning in the second portion of the encapsulant.

[0026] In another aspect of the present invention, the chip / first portion of encapsulant / discrete solder bump assembly described above is coated with a thin layer of the second portion of the encapsulant which is either lightly filled or completely devoid of filler material. Placement of the chip, solder reflow and adhesive cure follows as described above.

[0027] In another aspect of the present invention, there is provided a method for placing a flip-chip onto a substrate that avoids entrapment of gas bubbles or creation of voids. The chip, having the first portion of encapsulant thereon, is oriented at an angle to the substrate having the second portion thereon, then pivoted about the first point of contact until the solder bumps on the chip are in contact with the solder pads on the substrate, creating an underfill of encapsulant material as the chip is pivoted while expelling the gas from between the chip and substrate.

[0028] Another aspect of the present invention provides a chip with underfilling encapsulant pre-coated and pre-assembled on the chip for assembly to a substrate, wherein the encapsulant consists of more than one layer, each layer performing one or more distinct functions such as attachment, stress distribution, electrical redistribution, reworkability, adhesion, or other functions. The bulk of the encapsulant, consisting of one or more layers, is applied and partially or fully hardened prior to assembly of the chip on the substrate. Holes therein which expose metallized contact pads on the active surface of the chip are subsequently filled with solder or an electrically conductive adhesive as previously described to create an encapsulated subassembly. Then a flux adhesive is applied between the chip / encapsulant / solder bump combination and the substrate which can be fully hardened after or when the chip / encapsulant / solder bump combination is placed on the substrate and the solder is reflowed.

[0029] Removal of the chip from the substrate is made possible by incorporating in the pre-coated multi-layer encapsulant a polymer layer that can be remelted even after the chip has been assembled to the substrate. Remelting the solder and the polymer encapsulant layer allows removal of the chip for repair or replacement after assembly or for test and burn-in of the chip prior to final assembly. Thus the chip can be disassembled from the substrate without damage to either chip or substrate.

[0030] In another aspect of the present invention there is provided a redistribution of the chip's electrical interconnection pads by incorporating in the precoated multilayer encapsulant an electrical redistribution layer comprising a thin printed circuit layer with electrical circuitry thereon. The interconnect pads on the chip are attached by solder bumps, conductive adhesive or wire bonds to the redistribution layer. The redistribution layer is subsequently encapsulated. Holes in the encapsulant expose metallized contact pads on the active surface of the redistribution layer. The holes are subsequently filled with solder as previously described. Then a flux adhesive layer is applied between the chip / encapsulant / redistribution layer subassembly and the substrate. The flux adhesive is applied remaining unhardened until the subassembly is placed on the substrate and the solder is reflowed.

Problems solved by technology

One obstacle to flip-chip technology when applied to polymer printed circuits is the unacceptably poor reliability of the solder joints due to the mismatch of the coefficients of thermal expansion between the chip, having a coefficient of thermal expansion of about 3 ppm / ° C., and the polymer substrate, e.g. epoxy-glass having a coefficient of thermal expansion of about 16 to 26 ppm / ° C., which causes stress build up in the solder joints.

Because the structural solder joints are small, they are thus subject to failures.

The underfill process, however, makes the assembly of encapsulated flip-chip printed wire boards (PWB) a time consuming, labor intensive and expensive process with a number of uncertainties.

After reflow, due to the close proximity of the chip to the substrate, removing flux residues from under the chip is such a difficult operation that it is generally not done.

These residues are known to reduce the reliability and integrity of the encapsulant.

The reflowing of the solder bump and then underfilling and curing the encapsulant is a multi-step process that results in reduced production efficiency;

To underfill a flip-chip assembly takes too long because the material must flow through the tiny gap between the chip and the substrate;

The flux residues remaining in the gap reduce the adhesive and cohesive strengths of the underfill encapsulating adhesive, affecting the reliability of the assembly; and

As the size of chips increase, the limiting effect of capillary action becomes more critical and makes the encapsulation procedure more time consuming, more susceptible to void formation and to the separation of the polymer from the fillers during application.

This method suffers from the need to reserve an area in the center of the substrate that is free of circuitry in order to provide an unused space for the hole.

It also does not eliminate the problems of entrapped air bubbles.

The limitation of this technique is that in order for the molten solder to readily wet the substrate metallization and also to allow the solder, through surface tension, to self-align the chip bumps to the substrate metallization pattern, the material must maintain very low viscosity during the reflow step.

But the viscosity of these materials is severely increased by the presence of the required inorganic fillers.

As a result, this approach has failed to produce a material that can serve as both the flux and the encapsulant with the required low coefficient of thermal expansion and high modulus for optimum reliability.

Unfortunately, the effect of the encapsulant bending the substrate and the chip causes its own new set of problems.

One such problem is that the bending makes the chips susceptible to cracking.

Another such problem is that the degree of stress relief is highly dependent on the flexibility of the under-lying substrate and is thus an unpredictable function of the design of the printed circuit.

Another limitation is that relying on such bending for stress relief on the solder joints prevents the placement of flip chips directly opposite one another on a double-sided printed circuit.

Another limitation of prior art flip-chip attachment is the difficulty of performing rework.

Chip removal, once underfill has been performed, is very destructive to both the printed circuit board and the chip.

Rework is almost impossible with prior art materials and processes.

Another limitation of the prior art is the expense of applying solder bumps to a chip.

This method suffers from 1) long deposition times, 2) limitations on the compositions of solder that can be applied to those metals that can be readily evaporated, and 3) evaporating the metals over large areas where the solder is ultimately not wanted.

Also, since most solders contain lead, a toxic metal, evaporation involves removal and disposal of excess coated lead from equipment and masks.

Electroplating is a slow and expensive process that also deposits the solder over large areas where the solder is ultimately not wanted.

This technique is limited to bump dimensions that can be readily stencil printed, so it is not practical in bump pitches of 25 microns or less.

Another limitation of the prior art is the difficulty in distributing electrical signals from the small dimension of the chip to the large dimensions of the substrates.

Today, this discrepancy is bridged by creating expensive redistribution layers on the printed circuit.

Few manufacturers are able to produce printed circuits at the tight dimensional tolerances required for redistribution, but those who are capable of doing so achieve this with significant production yield penalties.

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