Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

Abstract

Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a mixed technology, "smart power", integrated device containing power transistors and control logic and analog driving circuitry combined in a monolithic silicon chip.2. Description of the Prior ArtThe commercial success of so-called "smart power" integrated circuits, wherein the analog signal processing circuitry, the control logic circuitry and the output power devices are conveniently monolithically integrated in a single chip, originated and sprung from the overcoming of compatibility problems among the different fabrication processes relative to the different integrated devices, often necessarily operating under different supply voltages. Most often, even though non-exclusively, the power section of such integrated circuits employs VDMOS transistors which typically require a driving gate voltage level comprised between about 10 V-20 V.This makes difficult interfacing the power transistor (e.g. ...

AI Technical Summary

Benefits of technology

The CMOS structures formed by pairs of complementary LDMOS transistors, when provided with such an n-doped region by phosphorus implantation, become capable of operating with a supply voltage of about 20 V without requiring special precautions, such as "field plates", thus remaining advantageously compact.

In the case of an n-channel MOS transistor belonging to another type of CMOS structure, the n-doped region, obtained by phosphorus implantation in the drain area of the transistor, reduces the sensitivity to electrical stresses due to hot electrons, by acting as a "drain extension" region; this permits to the transistor to withstand a supply voltage of about 12 V.

In the case of an isolated collector, vertical PNP bipolar transistor, the additional n-doped r

Problems solved by technology

This makes difficult interfacing the power transistor (e.g. VDMOS) with the driving circuitry.

In "smart power" type integrated circuits, th

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