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Nickel plating method for surface of silicon nanowires

A technology of silicon nanowires and nickel plating, which is applied in the field of semiconductor microelectronics and nanoelectronics, can solve the problems of interface electromigration size effect, which cannot meet the shrinkage of device size, etc., and achieve the reduction of resistivity, contact resistance and performance and good structure

Inactive Publication Date: 2008-10-08
FUDAN UNIV
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  • Claims
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AI Technical Summary

Problems solved by technology

As the size of the device enters the nanometer scale and finally reaches the physical limit of 22 nanometers, the working principle of the device will be completely changed due to the influence of quantum effects and small size effects, and the original semiconductor materials and processes will not be able to meet the requirements of the device size. zoom out
Devices must rely on new semiconductor materials if they want to develop into a smaller nanometer field, that is, semiconductor nanowires and nanotubes; in addition, the interconnection in integrated circuits has experienced the development process from aluminum to copper, but today's most advanced copper interconnection There are still unresolved problems such as interface electromigration and size effects in the technology. The research and development of interconnect materials in the next generation of nanoelectronic devices integrated with nanowires and nanotubes is still in its infancy. Therefore, new nanoscale interconnect materials and related integration Technology research is also very urgent

Method used

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  • Nickel plating method for surface of silicon nanowires
  • Nickel plating method for surface of silicon nanowires
  • Nickel plating method for surface of silicon nanowires

Examples

Experimental program
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Effect test

Embodiment 1

[0021] (1) Preparation of silicon nanowires by thermal evaporation of SiO

[0022] The experimental device is a low-vacuum tube furnace (Hefei Kejing, GSL-1400X vacuum tube furnace), which consists of a tube-type heating furnace with a length of 75cm, a corundum tube with a diameter of 60cm and a length of 120cm, a bipolar vacuum pump, and a gas flowmeter. , the vacuum degree of the device can reach 10 -2 torr. Before the experiment, the quartz boat was cleaned with acetone and alcohol, rinsed with deionized water, dried, and then pushed into the end of the tube furnace. At the same time, the small porcelain boat filled with SiO was pushed into the middle of the tube furnace. Vacuum for 30min, at this time the vacuum degree in the furnace reaches 10 -2 torr, after the tube furnace reached 800°C at a heating rate of 15°C / min, Ar gas (purity: 99.999%) was introduced into the furnace at a flow rate of 60 sccm, and the furnace tube was rapidly heated at a heating rate of 20°C / mi...

Embodiment 2

[0030] The preparation and pretreatment of silicon nanowires are the same as in Example 1. The silicon nanowires from which the silicon oxide layer has been removed are ultrasonically dispersed and dropped on a polished silicon wafer. Argon ion sputtering equipment (Denton Discovery-18 sputtering system) is used as the sputtering equipment , the vacuum degree of the sputtering system is 5×10 -6 torr, with 9.1W sputtering power to nickel-plate the surface HF-treated silicon nanowires; set the sputtering time to 240s, the results are as follows image 3 Shown; after sputtering, the surface of silicon nanowires is coated with amorphous nickel particles, on this basis, it is annealed. Annealing is carried out in a tube furnace (Hefei Kejing, GSL-1400X vacuum tube furnace). Before annealing and heating up, a mechanical pump is used to pump the vacuum in the furnace tube to 10 -2 torr, then charge 5×10 4 Pa Ar gas is the protective gas and carrier gas, the Ar flow rate is 300sccm ...

Embodiment 3

[0032] The preparation and pretreatment of silicon nanowires are the same as in Example 1. The silicon nanowires from which the silicon oxide layer has been removed are ultrasonically dispersed and dropped on a polished silicon wafer. Argon ion sputtering equipment (Denton Discovery-18 sputtering system) is used as the sputtering equipment , the vacuum degree of the sputtering system is 10 -6 torr, with 9.1W sputtering power to nickel-plate the surface HF-treated silicon nanowires; set the sputtering time to 270s, the results are as follows Figure 4 Shown; after sputtering, the surface of silicon nanowires is coated with amorphous nickel particles, on this basis, it is annealed. Annealing is carried out in a tube furnace (Hefei Kejing, GSL-1400X vacuum tube furnace). Before annealing and heating up, a mechanical pump is used to pump the vacuum in the furnace tube to 10 -2 torr, then charge 1×10 5 Pa Ar gas is the protective gas and the carrier gas, the Ar flow rate is 100 s...

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Abstract

The invention relates to a method for plating nickel on the surface of a silicon nanometer wire. 3 to 5 percent of HF is adopted to eliminate the silica layer on the surface of silicon nanometer wire fabricated by oxide-assisted growth mechanism. An argon ion sputtering device is taken as a sputtering device, the surface metallization process of nickel is realized on the surface of the silicon nanometer wire, the anneal is performed under a certain temperature, and a silicon nanometer wire structure which has better structure and performance and has monocrystalline silicon kernel coated with metallic nickel thin film is obtained. The specific resistance of the silicon nanometer wire surface after being plated with the nickel is reduced greatly, thereby ensuring that the nanometer wire and the metal electrode can realize effective ohmic contact, the contact resistance is reduced, and in addition, the nickel plated high conductivity nanometer wire also has wide application foreground in the future interconnection technology.

Description

technical field [0001] The invention belongs to the technical field of semiconductor microelectronics and nanoelectronics, and in particular relates to a method for plating nickel on the surface of silicon nanowires. Background technique [0002] In the next few decades, as the traditional "top-to-bottom" microelectronics process is limited by classical physics theory, it will become more and more difficult to reduce the size of electronic devices by this process, but Moore's law points out that in microprocessing The number of transistors on a device will double within 18 months, and more and more unit circuits will be integrated on a chip, resulting in a continuous reduction in the size of semiconductor devices. As the size of the device enters the nanometer scale and finally reaches the physical limit of 22 nanometers, the working principle of the device will be completely changed due to the influence of quantum effects and small size effects, and the original semiconduct...

Claims

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Application Information

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IPC IPC(8): C23C14/16C23C14/35C23C14/58
Inventor 江素华陈扬文邵丙铣王炜戎瑞芬顾志光汪荣昌
Owner FUDAN UNIV
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