Method for reducing 4H-SiC intrinsic deep energy level defects

A deep-level and defect technology, applied in the field of microelectronic materials and devices, can solve the problems of lack of consideration of temperature and surface protection, affecting the quality of 4H-SiC single crystal, and unable to effectively reduce deep-level defects, so as to reduce damage. , the effect of reducing the precipitation of Si

Inactive Publication Date: 2010-01-06
XIDIAN UNIV
View PDF0 Cites 16 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the above theoretical analysis, it is proposed that high temperature annealing suppresses and reduces intrinsic deep level defects in 4H-SiC, but due to the lack of consideration of the time, temperature and surface protection of high temperature annealing, a series of problems such as Si precipitation on the surface of 4H-SiC are caused; The method of online growth to increase

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for reducing 4H-SiC intrinsic deep energy level defects
  • Method for reducing 4H-SiC intrinsic deep energy level defects
  • Method for reducing 4H-SiC intrinsic deep energy level defects

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0025] Example 1

[0026] Reference figure 1 , The present invention includes the following steps:

[0027] Step 1, pretreating the 4H-SiC material used.

[0028] Using 4H-SiC material produced by CREE company, its doping level is 10 18 cm -3 . First, passivate the surface of the 4H-SiC substrate with molten KOH at an etching temperature of 210°C and an etching time of 15s; then, clean the passivated wafer with acetone, methanol, and deionized water in sequence Clean; Finally, use RCA standard cleaning process to remove the oxide layer on the surface of the sample.

[0029] Step 2. Grow N on the substrate - Epitaxial layer.

[0030] Growing homogeneous N on the pretreated substrate by CVD method - Type epitaxial layer, the epitaxial layer doping is 1.1×10 15 cm -3 , The thickness is 10±0.1μm.

[0031] Step 3, the ion implantation barrier layer is made by a deposition method.

[0032] After the epitaxial wafer is cleaned by RCA standard, 100nm SiO is made on the front surface of the epit...

Example Embodiment

[0039] Example 2

[0040] Reference figure 1 , The present invention includes the following steps:

[0041] Step 1, pretreating the 4H-SiC material used.

[0042] Using 4H-SiC material produced by CREE company, its doping level is 10 18 cm -3 . First, passivate the surface of the 4H-SiC substrate with molten KOH at an etching temperature of 210°C and an etching time of 15s; then, clean the passivated wafer with acetone, methanol, and deionized water in sequence Clean; Finally, use RCA standard cleaning process to remove the oxide layer on the surface of the sample.

[0043] Step 2. Grow N on the substrate - Epitaxial layer.

[0044] Growing homogeneous N on the pretreated substrate by CVD method - Type epitaxial layer, the epitaxial layer doping is 1.1×10 15 cm -3 , The thickness is 10±0.1μm.

[0045] Step 3, the ion implantation barrier layer is made by a deposition method.

[0046] After the epitaxial wafer is cleaned by RCA standard, 200nm SiO is made on the front surface of the epit...

Example Embodiment

[0053] Example 3

[0054] Reference figure 1 , The present invention includes the following steps:

[0055] Step 1, pretreating the 4H-SiC material used.

[0056] Using 4H-SiC material produced by CREE company, its doping level is 10 18 cm -3 . First, passivate the surface of the 4H-SiC substrate with molten KOH at an etching temperature of 210°C and an etching time of 15s; then, clean the passivated wafer with acetone, methanol, and deionized water in sequence Clean; Finally, use RCA standard cleaning process to remove the oxide layer on the surface of the sample.

[0057] Step 2. Grow N on the substrate - Epitaxial layer.

[0058] Growing homogeneous N on the pretreated substrate by CVD method - Type epitaxial layer, the epitaxial layer doping is 1.1×10 15 cm -3 , The thickness is 10±0.1μm.

[0059] Step 3, the ion implantation barrier layer is made by a deposition method.

[0060] After the epitaxial wafer is cleaned by RCA standard, 100nm SiO is made on the front surface of the epit...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method for reducing 4H-SiC intrinsic deep energy level defects, which can be used for improvement on 4H-SiC material quality and application to devices. The particular process is as follows: (1) a 4H-SiC substrate is pretreated, and an N<-> extension layer grows on the front surface of the 4H-SiC substrate; (2) a layer of SiO2 is deposited on the N<-> extension layer and taken as a blocking layer for carbon ion injection; (3) the carbon ion injection with different energies and dosages is preformed for three times on the surface of the blocking layer; and (4) the 4H-SiC sample wafer after the three times of carbon ion injection is subjected to RCA cleaning and drying, and then annealing in a high-temperature environment in the presence of hydrogen and silane, the injected carbon ions are activated, and the treatment to the intrinsic deep energy level defects of the 4H-SiC material is completed. The actual measurement shows that the invention can effectively reduce the deep energy level defects in the 4H-SiC sample wafer, and can be used for improving the quality of the 4H-SiC material and promoting the performance of devices.

Description

technical field [0001] The invention belongs to the technical field of microelectronic materials and devices, and in particular relates to a method for reducing intrinsic deep-level defects in 4H-SiC through a carbon ion implantation annealing process, which can be used for improving the quality of 4H-SiC materials and application of devices. Background technique [0002] As a third-generation semiconductor material, SiC material has considerable advantages over the first-generation semiconductor materials represented by Si and the second-generation semiconductor materials represented by GaAs. Due to its large forbidden band width, it can be used in Working at a higher temperature is conducive to the preparation of high-power devices, and the large carrier saturation drift speed and mobility provide a good foundation for the response speed of the device. At present, the development of SiC devices has become a research hotspot in the field of semiconductor device circuits. ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/02C23C14/48C23C14/06C23C16/44C23C16/40C23C28/04
Inventor 贾仁需张玉明张义门郭辉王悦湖
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap