Method for preparing silicon-based high-mobility CMOS (complementary metal-oxide-semiconductor) provided with III-V/Ge channel

Abstract

The invention discloses a method for preparing a silicon-based high-mobility CMOS provided with an III-V / Ge channel. The method comprises steps as follows: a germanium layer is grown on a silicon substrate; a low-temperature nucleation gallium arsenide layer, a high-temperature gallium arsenide layer, an on-growth semi-insulating InGaP (gallium indium phosphide) layer and a gallium arsenide cover coating are sequentially grown on the germanium layer after the first annealing, so that a sample is formed; the gallium arsenide cover coating of the sample is subjected to a gallium arsenide polishing process, and a nMOSFET (metal oxide semiconductor field effect transistor) structure is grown after the sample is subjected to secondary annealing; an area is selected on the surface of the nMOSFET structure for ICP (inductively coupled plasma) etching, downward etching from the nMOSFET structure to the germanium layer is performed to form a groove, and silicon dioxide layers are grown in the groove and on the surface of the nMOSFET structure in a PECVD (plasma enhanced chemical vapor deposition) manner; the area selected for etching is subjected to ICP etching again from the silicon dioxide layers to the germanium layer, and a groove is formed; the sample is cleaned, and a germanium nucleating layer and a germanium top layer are grown in the groove with an ultra-high vacuum chemical vapor deposition method; the germanium top layer is polished, and a part of silicon dioxide layers on the nMOSFET structure are removed; and the CMOS process of source, drain and grid electrodes is performed on the nMOSFET structure and the germanium top layer, so that the preparation of the device is finished.

Description

technical field [0001] The invention relates to the field of microelectronics, combines ultra-high vacuum chemical vapor deposition with MOCVD, and uses high aspect ratio confinement technology to realize simultaneous integration of silicon-based high-mobility III-V / Ge channel materials, and is applied to silicon-based III-V / Ge channel CMOS devices. Background technique [0002] The feature size drops to 22nm node, and the integrated circuit technology based on silicon CMOS technology follows Moore's law to achieve the purpose of increasing the working speed of the chip, increasing the integration level and reducing the cost by reducing the feature size of the device, and difficulties have arisen. Factors such as the increase in the cost of the nanofabrication process, the short-channel effect that reduces the gate control capability, and the limitation of the mobility of the silicon material itself negate the possibility of continuing to shrink the feature size of the devi...

AI Technical Summary

Problems solved by technology

Another solution to solve the III-V N-type channel and germanium P-type channel is to use silicon-based selective epitaxy, but the quality of III-V or germanium materials obtained by selective epitaxy is not ideal (micron size), The possibility of realizing this scheme remains to be investigated; at the same time, the extremely small-sized selected area epitaxy has gained great attention in recent years through the high aspect ratio trapping (ART) (J.S.Park et al, Appl.Phys.Lett.90, 052113, 2007), in the SiO2 trench, the epitaxial material is grown along the crystal plane (parallel to the trench direction) composed of {311} and {111} crystal groups, and the misalignment at the Si-Ge interface Misalignment defects generally extend along the growth direction of the epitaxial layer

However, the integration of silicon-based high-mobility N and P channels through this scheme has not yet been realized.

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