Low-dislocation-density high-reliability high-low-voltage CMOS self-alignment double-well process method and device

Abstract

The invention discloses a low-dislocation-density high-reliability high-low-voltage CMOS self-alignment double-well process method and device. The method comprises the following steps: 1) forming a low-defect-density high-voltage N-type well and a low-voltage N-type well, 2) forming a self-aligned P-type well, 3) being compatible with high voltage and low voltage, and being compatible with thick and thin gate oxide structures, and 4) being compatible with a multi-layer metal interconnection structure. The device comprises a substrate, a high-voltage N-type well, a low-voltage N-type well, a self-aligned P-type well, an LOCOS field oxide layer, a low-voltage MOS thin gate oxide layer, a gate polycrystal layer, a P-type MOS lightly doped source-drain injection region, a side wall protection layer, a P-type MOS source-drain injection region, a polycrystal layer, an oxygen-nitrogen dielectric layer, an N-type MOS source-drain injection region, a high-voltage MOS thick gate oxide layer, a gate polycrystal layer top oxygen-nitrogen dielectric protection layer, a silicon / polycrystalline silicon-metal layer M1 interlayer contact hole, a silicon / polycrystalline silicon / field oxide-metal layer M1 interlayer ILD medium planarization layer and the like. According to the invention, the dislocation defect density of the high-voltage well region is precisely controlled, and the reverse bias electric leakage of the isolation PN junction of the high-voltage well region is effectively inhibited.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a low dislocation density high reliability high and low voltage CMOS self-aligned double well process method and device. Background technique [0002] In the manufacturing process of CMOS / BiCMOS analog integrated circuits, more and more attention is paid to the low defect and high reliability of the well region that affects the performance of MOS devices. In particular, the sub-micron CMOS analog process compatible with high and low voltage requires that the process can provide not only a deep junction well region with low leakage and high voltage resistance, but also a shallow junction well region with low power consumption and low operating voltage. Especially for high-performance and high-voltage devices, it is required to use high-temperature and long-time well pushing operations to ensure uniform and stable impurity distribution in the well region, and at the...

AI Technical Summary

Problems solved by technology

There are basically no macro dislocation defects in the normal initial single crystal silicon wafer, but after the silicon wafer undergoes a subsequent high-temperature process, macro dislocations can be formed in the silicon wafer, and the dislocation defect multiplication phenomenon will also occur

This will lead to many problems such as device performance degradation, circuit reliability, etc.

For example, the dislocation density in the edge region of the well directly determines the strength of the reverse bias leakage current of the isolated PN junction, which ultimately affects the stability and reliability of integrated circuit devices, etc.

Images