Single electron memory having carbon nano tube structure and process for making it

Abstract

The invention relates to a single electron memory having carbon nano tube structure and process for making it. The memory uses the semi-conductive GaAs as substrate, a buffer layer is prepared on the substrate, a Si-containing delta doping GaAs thin layer is prepared on the buffer layer, a nano line is made by etching processing in the delta doping GaAs layer, one end of the nano line is data cable pin, and there are two control grids parallel to the two sides of the namo lines at each side of them. The memory unit is the part of the namo line which is longer the control grid and extending into between the two electrodes of the carbon nano transistor. By controlling several dozens or several electrons, the normal operation of the memory can be realized and without the influence of the random background charges, thus solving the problems such as stability, power consumption, radiation and grid leakage current faced in the development of the traditional memories, the invention also realizes the super-high density information storage under the low power consumption condition.

Description

technical field [0001] The invention relates to a memory device, in particular to a single-electron memory with a carbon nanotube structure and a preparation method. Background technique [0002] Memory accounts for 40% of the world's semiconductor market. Semiconductor products other than memory are updated every 2 years, while memory is a generation every 18 months. Taking the development of dynamic memory (DRAM) as an example, in 1988 Japan The line width of the lines on the silicon chip reached 0.8 microns, and the 4Mb DRAM came out, thus entering the era of ultra-large-scale integration ULSI; in 1992, the 16Mb chip with a line width of 0.5 microns was put into production; in 1994, the 64Mb chip with a line width of 0.35 microns was launched. Chip production; 0.13-micron 4Gb DRAM will soon be realized. However, maintaining the trend of continuous scale reduction is facing an extremely serious challenge, that is, the capacitance in the storage unit cannot be too small. I...

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Problems solved by technology

However, maintaining the trend of continuous scale reduction is facing an extremely serious challenge, that is, the capacitance in the storage unit cannot be too small. If the capacitance is too small to provide enough electrons to the amplifier, the entire memory will be flooded by noise, and the The reliability of information storage cannot be guaranteed; at the same time, the number of electrons in each storage unit will become smaller and smaller with the further improvement of the integration of storage devices, and the MOS field effect transistors in the memory will gradually become unstable.

[0003] In order to continue to maintain the high-speed development of memory devices, people hope to replace traditional memory devices with single-electron memory devices. Metal-oxide-semiconductor field-effect transistor (MOSFET) is used to prepare single-electron dynamic random access memory (J.Appl.Phys.2000, 12, 8594), although this device solves several problems such as power consumption that plague traditional memories, but This device uses the MTJ / MOSFET structure, which limits the further improvement of the integration level, because the size of the MOSFET cannot be too small, otherwise the number of working electrons is too small, which will affect the stability of the device

If the gate of the device is divided into three parts, and the split gate MOSFET is used to reduce the charge required for operation, the integration of the device is lower

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