Highly selective doped oxide etchant

Abstract

Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in the construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally with an inorganic acid, and a pH of 1 or less.

Description

FIELD OF THE INVENTION [0001] The invention relates generally to semiconductor and MEMS processing methods and constructions, and more particularly to methods of forming capacitor structures in memory devices. BACKGROUND OF THE INVENTION [0002] A dynamic random access memory (DRAM) device is commonly used in electronic systems to store data. A typical DRAM device will have one region corresponding to a memory array and another region peripheral to the memory array in which logic or other circuitry is to be formed. Each memory cell generally consisting of a capacitor coupled through a transistor gate electrode or wordline stack to a bit or digit line. [0003] Continuing advances in miniaturization and densification of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. With shrinkage of the cell size, maintaining a sufficient amount of cell charge storage capacitance is a challenge in a DRAM construction. [0004] Several techniques ha...

AI Technical Summary

Benefits of technology

[0026] The openings can extend in an array comprising rows and columns, and the silicon nitride layer can be patterned to extend between and connect pairs of the rows of the conductive structure array. Following the selective removal of the doped oxide material, the method can further include forming a capacitor dielectric layer over the exposed inner and outer surfaces of the conductive container structures, and forming a second conductive material layer over the capacitor dielectric layer. In embodiments of the construction, the doped oxide is composed of a phosphosilicate glass, the silicon nitride comprises a low temperature silicon nitride (e.g., HCD SiN), and the conductive material layer comprises titanium nitride.

Problems solved by technology

With shrinkage of the cell size, maintaining a sufficient amount of cell charge storage capacitance is a challenge in a DRAM construction.

A draw-back of the foregoing process is that exposure of both the interior and exterior surfaces of a “free-standing” container, particular a container having a high aspect ratio, can render the container structurally weak and subject to collapse during exposure to a wet-etch process to remove the doped oxide material from adjacent the bottom electrode.

Conventionally, the SiN layer 24 is formed using a high temperature deposition process at about 700-780° C. However, high process temperatures can be detrimental, and the trend for future generation devices is the use of low temperature depositions of about 600° C. or less due to thermal budget limitations and to avoid damaging existing features.

However, the etch rate is relatively slow at about 2,000 Å / minute, which impacts processing throughput.

Thus, current H2O:HF etch chemistries for high temperature silicon nitrides do not provide the selectivity of doped oxide relative to low temperature silicon nitrides that is needed in the fabrication of container constructions.

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