InGaZnO thin film transistor and manufacturing method thereof

Abstract

The invention discloses an InGaZnO thin film transistor and a manufacturing method thereof. The transistor comprises a substrate; a buffer layer is arranged on the substrate; an InGaZnO thin film is arranged on the buffer layer; a passivation layer, source leakage contact electrodes and a gate dielectric layer are arranged on the InGaZnO thin film; and a gate electrode is arranged on the gate dielectric layer. A top gate structure is adopted, the parasitic capacitance is reduced, the equal proportion reduction ability is enhanced, the driving voltage of the gate is reduced, arsenic ions or phosphorus ions are adopted as implanted ions, annealing treatment is carried out on the source and drain area after ion implantation, a low-resistance N-type heavy doping zone is obtained, and the transistor thus has the advantages of low contact resistance and good thermal stability. The InGaZnO thin film transistor and the manufacturing method thereof can be widely applied to the semiconductor field.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to an indium gallium zinc oxide thin film transistor and a manufacturing method thereof. Background technique [0002] With the development and promotion of the next-generation new AMOLED active display, metal oxide thin film transistors have received more and more attention and research, among which bottom-gate indium gallium zinc oxide (a-InGaZnO) thin film transistors (TFT) are the most representative. However, the bottom gate type structure has the disadvantages of large parasitic capacitance and proportional scaling capability, and it is difficult to apply to the integration of peripheral circuits to realize the system integration SOP of the display panel. A small number of scholars have carried out research on the self-aligned top-gate structure with small parasitic capacitance. However, in the method of source-drain doping, hydrogen is generally used (J.Park et.al, Appl.Phys.Le...

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Problems solved by technology

However, the bottom gate structure has the disadvantages of large parasitic capacitance and the ability to scale down, making it difficult to apply to the integration of peripheral circuits to achieve the system integration SOP of the display panel

A small number of scholars have carried out research on self-aligned top-gate structures with small parasitic capacitances. However, in the method of source-drain doping, hydrogen is generally used (J.Park et.al, Appl.Phys.Lett., 93, 053501 , 2008) or argon (B.Du Ahn et.al, Appl.Phys.Lett., 93, 203506, 2008) plasma treatment to form a highly conductive region, but such transistors have stability problems, especially thermal stability Poor problem: Because the hydrogen element is lighter, it is easier to diffuse from the source and drain regions to the channel, and the channel becomes low resistance, which short-circuits the device; the use of argon plasma treatment can form oxygen vacancy defects to reduce the resistivity, but oxygen The vacancy defect is relatively unstable, as long as a slight heat treatment is performed, the carrier concentration will change significantly, resulting in a sharp decline in device performance

Therefore, the problem of thermal stability has always been a major problem faced by a-InGaZnO TFT

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