Perovskite/crystalline silicon laminated solar cell structure
A technology of perovskite cells and laminated solar cells, which is applied in the field of solar cells, can solve the problems that the current cannot be directly connected, the laser opening technology is complicated, and it is difficult to apply.
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Embodiment 1
[0026] The perovskite / crystalline silicon stacked solar cell structure includes: a bottom cell and a perovskite top cell; the bottom cell is a crystalline silicon-PERC bottom cell; the perovskite top cell includes a perovskite cell carrying current Sub-transport layer A8, perovskite absorption layer 9, perovskite cell carrier transport layer B10, transparent conductive film 11 and top electrode grid line 12; the top electrode grid line 12 is located at the top of the transparent conductive film 11;
[0027] The structure of the crystalline silicon-PERC bottom cell from the bottom to the top is the back electrode gate line 1, passivation layer A2, passivation layer B3, p-type silicon wafer 13, n-type doped emitter 14, ultra-thin Tunneling dielectric layer 6 and heavily doped polycrystalline silicide film 7; the back electrode gate line 1 is embedded in the passivation layer A2 and the bottom of the passivation layer B3 is in contact with the p-type silicon chip 13; the n-type do...
Embodiment 2
[0032] The perovskite / crystalline silicon laminated solar cell structure includes: a bottom cell and a perovskite top cell; the bottom cell is a crystalline silicon-PERT bottom cell; the perovskite top cell includes a perovskite cell carrying current Sub-transport layer A8, perovskite absorption layer 9, perovskite cell carrier transport layer B10, transparent conductive film 11 and top electrode grid line 12; the top electrode grid line 12 is located at the top of the transparent conductive film 11;
[0033] The structure of the crystalline silicon-PERT bottom cell from the bottom to the top is the back electrode gate line 1, passivation layer A2, passivation layer B3, n-type silicon wafer 4, p-type doped emitter 5, ultra-thin Tunneling dielectric layer 6 and heavily doped polycrystalline silicide film 7; the back electrode gate line 1 is embedded in the passivation layer A2 and the bottom of the passivation layer B3 is in contact with the n-type silicon wafer 4; the p-type do...
Embodiment 3
[0039] The bottom cell is a planar n-PERT cell, the surface is made of silicon oxide, and the thickness of phosphorus-doped amorphous silicon is 20nm. After rapid annealing at 700°C for 10-300s, a tunnel junction is formed, and the contact resistivity is 10-20mΩ.cm2. Square resistance is 1000Ω / sq. An electron transport layer (which can be but not limited to TiO2) with a thickness of 1-300 nm is sequentially prepared on the tunnel junction 2 , SnO 2 , ZnO, PCBM, C 60 , Nb 2 o 5 , SrTiO 3 , ICBA, ICTA and other materials), the thickness of 50 ~ 1500nm perovskite film (ABX 3 , where A is MA (methylamine), FA (formamidine), 5-AVA (5-ammonium isovalerate) or CS and combinations thereof, and B is Cu, Ni, Fe, Co, Mn, Cr, Cd, Sn , Pb, Pd, Ge, Eu or Yb and combinations thereof, X is I, Br or Cl or combinations thereof), a hole transport layer with a thickness of 1 to 300 nm (can be but not limited to spiro-OMeTAD, NiO x , CuI, CuSCN, NiO x , PEDOT:PSS, CuCSN, Graphene oxide, Cu...
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