Growth of GaAs expitaxial layers on Si substrate by using a novel GeSi buffer layer

Abstract

This invention provides a process for growing Ge epitaixial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and subsequently growing a GaAs layer on Ge film of the surface of said Ge epitaixial layers by using metal organic chemical vapor deposition (MOCVD). The process comprises steps of, firstly, pre-cleaning a silicon wafer in a standard cleaning procedure, dipping it with HF solution and prebaking to remove its native oxide layer. Then, growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.8 μm on said Si substrate by using ultra-high vacuum chemical vapor deposition under certain conditions. Thus, many dislocations are generated and located near the interface and in the low of part of Si0.1Ge0.9 due to the large mismatch between this layer and Si substrate. Furthermore, a subsequent 0.8 μm Si0.05Ge0.95 layer, and / or optionally a further 0.8 μm Si0.02Ge0.98 layer, are grown. They form strained interfaces of said layers can bend and terminate the propagated upward dislocation very effectively. Therefore, a film of pure Ge is grown on the surface of said epitaixial layers. Finally, a GaAs epitaixial layer is grown on said Ge film by using MOCVD.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to a process for manufacturing semiconductor structure or devices, more particular for growing a high quality Ge film on Si substrate using a novel GeSi buffer method and additionally growing a high quality Group III-V, such as GaAs epitaixial layer on the grown Ge / SiGe / Si substrate. [0003] 2. Description of Related Art [0004] The growth of high quality GaAs or other III-V compound semiconductors on silicon substrate is recognized as a desirable goal for the fabrication of advanced semiconductor devices. Specific advantages of this combinations of materials include the availability of GaAs with high electron mobility and optical activity on a silicon substrate with improved mechanical strength and thermal conductivity over that obtainable with GaAs substrate. In addition, the growth of high quality GaAs on silicon offers the possibility of monolithically integrating GaAs and silicon devices fo...

AI Technical Summary

Benefits of technology

[0012] A first object of this invention is to solve hereinabove problems, as for growing Ge epitaxy on Si by using a novel method, including how to lower the thickness of Ge epitaixial layers, to flatten the surface roughness induced from high Ge-composition epitaixial layers without help of CMP, and to lower the high defects density due to lattice mismatch.

[0014] The conception of the process for this invention is, firstly growing a high Ge-composition epitaixial layer, such as Si0.1Ge0.9 in a thickness of 0.5˜0.8 μm on Si substrate, in which many dislocations are generated and located near the interfaces and in the low of part of this layer due to the large mismatch between this layer and Si substrate. Subsequently growing two or three layers of more high Ge-composition epitaixial layers, such as Si0.05Ge0.95 and / or Si0.02Ge0.98 in a thickness of 0.5˜0.8 μm. The formed strained interfaces between said layers can bend and terminate the propagated upward dislocation from the first layer very effectively. Then, growing a final film of pure Ge on herein epitaixial layer and a total epitaixial thickness is of only several micrometers, such as below 3 micrometer.

[0015] The in-situ high temperature annealing for each layers is performed in growing process therein, and carried out under the temperature of from 650 to 800° C., and 15˜30 minutes to further promote the quality of single crystalline of the Ge film.

Problems solved by technology

In addition, the growth of high quality GaAs on silicon offers the possibility of monolithically integrating GaAs and silicon devices for advanced electronic components.

However, one of the key limitations in the implementation of device structure based on heteroepitaixial GaAs on silicon has a 4.0% difference in lattice constant and additional intrinsic thermal conductivity difference between the two different materials.

This lattice mismatch leads to the formation of a network of misfit dislocation at the heterointerface and high density threading dislocation in the epitaixial layers.

Furthermore, due to large difference between thermal expansion coefficient of GaAs and that of Si, it is difficult to remove the additional dislocation induced during annealing, thus, these arts obviously are not deemed to be used for fabricating of high performance device.

However, these arts obviously make some problems, such as high fabricating cost and no large scale of GaAs epitaxy on Si substrate to be obtained.

However, it is difficult to grow a high quality ZnSe on Si, and the small thermal conductivity of ZnSe is disadvantageous for fabricating of device, thus, the utilization of this invention is in the presence of some problems to be solved.

However, it is with high fabricating cost and low productivity for growth by applying molecule beam epitaxy (MBE), and additionally it is with small thermal conductivity of STO film, which is disadvantageous for heat diffusion of device, thus, the utilization of this invention totally is in the presence of some problems to be solved, too.

As for applying the technique in using Ge composition graded buffer for growing SiGe epitaxy, which is disclosed in “Novel dislocation structure and surface morphology effects in relaxed Ge / SiGe(graded) / Si structures” from E. A. Fitzgerald et al. mentioned above, wherein graded Si1-xGex is applied as interlayer for the growth of GaAs epitaxy on Si due to almost the same lattice constant and thermal expansion coefficient for the two different materials, this technique has comparatively wide field in application, but is also in the presence of some problems to be overcome.

Wherein, high surface roughness due to thick epitaixial layer and cross hatch pattern will increase the fabrication cost of epitaxy and cause difficulties in device producing.

As for removing cross hatch pattern, chemical-mechanical polishing (CMP) is subjected to solve these problems in above-mentioned references and patents, but it increases additional cost and causes difficulties in processing substantially.

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