45results about How to "Improving problems with implanted gate dielectrics" patented technology

The invention discloses a SiGe base vertical channel strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a manufacturing method. The method comprises the following steps of: manufacturing a SiGe HBT (Heterojunction Vipolar Transistor) device at a bipolar device area on a Si substrate sheet; etching an active area of an NMOS (N-Channel Metal Oxide Semiconductor) device; extensionally growing five layers of materials at the area so as to form the active area of the NMOS device; manufacturing the NMOS device; etching an active area of the PMOS (P-Channel Metal Oxide Semiconductor) device; extensionally growing three layers of materials at the area so as to form the active area of the PMOS device; forming a virtual grid and accomplishing the manufacturing of the PMOS device; and forming the SiGe base vertical channel strain BiCMOS integrated device and a circuit. The characteristics that the electronic mobility rate at the vertical direction and the hole mobility rate at the horizontal direction of the SiGe material are higher than that of the relaxation Si are utilized; and through a low temperature process, a circuit of the performance-enhanced SiGe base vertical channel strain BiCMOS integrated device is manufactured.

The invention discloses a bi-polycrystal SOI (Silicon On Insulator) Bi CMOS (Complementary Metal Oxide Semiconductor) integrated device with a SiGe clip-shaped channel and a preparation method of the device. The preparation method comprises the steps of conducting epitaxy on a collector region of a bipolar device on an SOI substrate, preparing a deep-trench isolator, a base window and base polycrystal, conducting epitaxy on a SiGe base region and a Poly-Si emitter region to form a SiGe HBT (Heterojuntion Bipolar Transistor) device; conducting photoetching on an active region of an NMOS (N-Channel Metal Oxide Semiconductor) device, growing five layers of materials on the region in an epitaxial manner to form the active region of the NMOS device so as to prepare an NMOS device; conducting photoetching on an active region of a PMOS (P-Channel Metal Oxide Semiconductor) device, growing three layers of materials in an epitaxial manner in the region to form the active region of the PMOS device, preparing a virtual grid electrode, and injecting by utilizing a self alignment process so as to form the drain electrode and the source electrode of the PMOS device; etching a virtual grid to prepare the PMOS device, and thus forming the Bi CMOS integrated with a conducting channel being 22-45nm and a circuit of an MOS (Metal Oxide Semiconductor) device, wherein the device and the circuit are based on the self alignment process. According to the preparation method, the self alignment process is adopted, and the characteristic of the anisotropism of the mobility ratio of strain SiGe material is utilized sufficiently, so that a bi-polycrystal SOI strain Bi COMOS integrated circuit with SiGe clip-shaped channel is prepared, and the performance of the circuit is enhanced.

The invention discloses a double poly-crystal plane strain BiCMOS integrated device based on a SOI (Silicon On Insulator) substrate and a preparation method. The preparation method comprises the following steps: preparing a deep slot isolator on the SOI substrate; forming a collector contact region, a nitride side wall and a base region window; growing SiGe and Poly-Si on the base region, thereby forming a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a slot on a NMOS (N-channel Metal Oxide Semiconductor) device active region, preparing a grid dielectric layer and a grid poly-crystal on the NMOS device active region, thereby forming a NMOS device; etching a slot on a PMOS (P-channel Metal Oxide Semiconductor) device active region and preparing a drain and a grid on the PMOS device active region, thereby forming a PMOS device; and photo-etching a lead, thereby preparing a BiCMOS integrated device and a circuit. According to the preparation method, a BiCMOS integrated circuit with an enhanced property is prepared by adopting a self-aligning technology and fully utilizing the characteristics that the electronic mobility of a spreading strain Si material is higher than that of a semiconductor Si material and the hole mobility of a compressive strain SiGe material is higher than that of the semiconductor Si material.