Consumption current is reduced for a
voltage regulator in
sleep mode. In normal
operation mode, a sub-
regulator circuit is ceased from operating according to a power-down
signal, which allows an operation
amplifier to compare between a reference
voltage outputted from a reference
voltage circuit and a monitor voltage generated by a voltage-dividing circuit. Based on a detection voltage as a comparison result, a PMOS is controlled to regulate an internal power voltage such that the monitor voltage becomes equal to the reference voltage. In
sleep mode, the reference voltage circuit and
operational amplifier is ceased from operating, to
start up the sub-
regulator circuit. A slight current, restricted by a resistance, flows through a PMOS of the sub-regulator circuit. The same magnitude of current is supplied from the PMOS constituting a
current mirror to a PMOS, etc. of a threshold-voltage output circuit. The
threshold voltage, at a node between the PMOS constituting the
current mirror and the PMOS of the threshold-voltage output circuit, is power-amplified by a voltage follower and outputted through an output terminal.