Hafnium-based oxide high k gate dielectric layer and energy band adjustment and control method of hafnium-based oxide high k gate dielectric layer

Abstract

The invention relates to a hafnium-based oxide high k gate dielectric layer and an energy band adjustment and control method of the hafnium-based oxide high k gate dielectric layer. The gate dielectric layer contains HfO2 and Gd2O3; and the atomic ratio Gd / (Gd plus Hf) is 0-30 percent and is not equal to 0. The energy band adjustment and control method of the hafnium-based oxide high k gate dielectric layer comprises the following steps of: respectively placing a cleaned quartz plate substrate and a cleaned monocrystalline Si chip substrate into a radio-frequency magnetic control co-sputtering plating system and co-sputtering the Gd2O3 and the HfO2 onto the substrates under the mixed atmosphere of argon and oxygen; the sputtering power of the HfO2 is 50-120W; the sputtering power of the Gd2O3 is 0-90W and is not equal to 0, and the sputtering air pressure is 0.5-3 Pa; the sputtering time on a quartz plate is 1-1.5h; the thickness of the gate dielectric layer is 100-140 nm; the sputtering time on a Si chip is 3-20 minutes; and the thickness of the gate dielectric layer is 3-25 nm. The Gd2O3 has the energy band adjustment and control effect on the HfO2 so as to facilitate reducing the leakage current of the hafnium-based oxide gate dielectric layer.

Description

technical field [0001] The invention relates to a hafnium-based oxide high-k gate dielectric layer and an energy band regulating method thereof. Background technique [0002] Since the birth of the first integrated circuit in 1958, the integration level of integrated circuits has doubled every eighteen months according to Moore's law. Its basic unit - metal oxide semiconductor field effect transistor (MOSFET, metal oxide semiconductor field effect transistor) The feature size, gate line width, and gate dielectric layer thickness are also shrinking in proportion. When silicon-based integrated circuit technology develops to 32nm technology node and below, the equivalent oxide thickness (EOT, equivalent oxide thickness) suitable for high-speed, low-voltage, low-power CMOS devices will be less than 1nm. The traditional gate dielectric is SiO 2 , whose dielectric constant is 3.9. Under the action of quantum tunneling effect, the gate leakage current will increase with SiO 2 T...

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Problems solved by technology

[0004] Although hafnium-based oxides have been successfully applied to Intel's 45nm technology node, compared with the nearly perfect silicon dioxide gate dielectric, hafnium-based oxide gate dielectrics still have the problem of small band gap and band bias. shift (relative to the substrate such as Si-based, Ge-based, etc.)

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