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A high threshold voltage normally-off high electron mobility transistor and its preparation method

A technology with high electron mobility and high threshold voltage, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve the problem of small gate withstand voltage and threshold voltage, difficulty in controlling the uniformity of gate etching depth, fluorine ion Distributed thermal stability and performance reliability problems are difficult to overcome, and achieve the effect of large conduction current density

Active Publication Date: 2021-12-31
DALIAN UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The groove gate scheme weakens or directly cuts off the 2DEG by partially or completely etching away the AlGaN barrier layer, so as to obtain normally-off operation. This scheme requires precise etching of the barrier layer. For large-area devices, the gate etching depth is uniform The fluorine ion implantation gate scheme can achieve the purpose of normally-off operation by using negatively charged fluorine ions to repel 2DEG, but in the process of application and promotion, the thermal stability and performance reliability of the fluorine ion distribution in the device are difficult Overcoming; the gate p-type capping layer is a better technical solution. This technology retains a good 2DEG channel, and uses its additional built-in electric field to raise the conduction band of the 2DEG channel interface to above the Fermi level, thereby obtaining a normally-off type operation, this technical solution can obtain a higher on-current density, which is suitable for industrialization promotion. At present, the main problem is that the gate withstand voltage and threshold voltage are relatively small

Method used

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  • A high threshold voltage normally-off high electron mobility transistor and its preparation method
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  • A high threshold voltage normally-off high electron mobility transistor and its preparation method

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Embodiment 1

[0054] The specific implementation process of this patent application is as follows:

[0055] Step ①: wafer growth.

[0056] AlN or AlGaN superlattice nucleation layer, 2-10μm GaN or GaAs epitaxial layer, 5-100nm AlGaN, InAlN, AlN or AlGaAs barrier layer (where the Al composition is 0.05-0.3), 30-100nm p-GaN or p-InGaN or p-AlGaN gate capping layers, such as figure 2 , image 3 shown.

[0057] Step ②: Etching the epitaxial layer structure.

[0058] Use semiconductor lithography technology and etching technology to make device mesas, and use semiconductor etching technologies such as inductively coupled plasma (ICP) or reactive ion etching (RIE) based on Cl-based gases to etch the surface by 300-800nm ​​to achieve Countertop isolation. Repeat this step to etch away the barrier layer in the source and drain regions to form grooves; further etch away the p-type capping layer outside the gate region, such as Figure 4 shown. Among them, the semiconductor photolithography ...

Embodiment 2

[0066] The specific implementation process of this patent application is as follows (detailed parameters and steps):

[0067] Step ①: GaN structure epitaxial growth.

[0068] A 100nm AlGaN superlattice nucleation layer, a 2μm GaN epitaxial layer, a 20nm AlGaN barrier layer (Al composition is 0.25), and a 50nm p-GaN cap were sequentially grown on a 6-inch p-type Si substrate by MOCVD equipment layer. The structure and size of the device are designed as follows: the distance between the source and the gate of the device is 2 μm, the length of the gate is 3 μm, the width is 200 μm, the length of the field plate extending from the gate to the drain is 1 μm, and the distance between the gate and the drain is 10 μm. The electrode area is 200×200μm 2 .

[0069] Step ②: Etching the epitaxial layer structure.

[0070] Using semiconductor lithography technology, the specific process is:

[0071] (1) Evenly spin coat the sample with AZ5214 photoresist at a rate of 4000r / min for 30s;...

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Abstract

A high threshold voltage normally-off high electron mobility transistor and a preparation method thereof belong to the technical field of semiconductor devices. Technical solution: The nucleation layer and the epitaxial layer are grown sequentially on the substrate. Above the epitaxial layer are the barrier layer, source and drain. The barrier layer and the epitaxial layer form a heterojunction structure. The contact interface between the two is formed by the polarized charge Two-dimensional electron gas is induced, the passivation layer is above the barrier layer, the gate cap layer is above the gate barrier layer, and the oxide dielectric layer is formed by surface plasma oxidation technology or directly deposited on the gate cap layer. layer or multiple gate dielectric insertion layers, the top of the gate dielectric insertion layer is a gate, the gate is in contact with the passivation layer, and a field plate extends from the gate to the drain on the passivation layer. Beneficial effects: the present invention realizes the normally-off device type while maintaining a large on-current density; by increasing the conduction band position of the barrier layer, the gate withstand voltage and threshold voltage of the normally-off device are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, in particular to a high-threshold voltage normally-off high electron mobility transistor and a preparation method thereof. Background technique [0002] Following the first-generation semiconductor materials (Ge, Si, etc.) and the second-generation compound semiconductor materials (GaAs, InP, etc.), gallium nitride (GaN), as an important representative of the third-generation new wide-bandgap semiconductor materials, has developed rapidly. And become the frontier and hotspot of research in the field of power semiconductors. GaN-based (mainly GaN, including GaN, AlN, InN and their composition combinations, etc.) semiconductor materials have large band gap, high electron saturation velocity, high temperature and high pressure resistance, and radiation resistance, which can make up for the second The lack of first and second generation semiconductor materials has broad application pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/20H01L29/41H01L21/335H01L29/778
CPCH01L29/66462H01L29/7786H01L29/2003H01L29/41H01L29/1066H01L29/42376H01L29/42356H01L29/41766H01L29/513H01L21/28593H01L21/0254H01L21/0262H01L21/28575H01L21/30621H01L21/7605H01L21/765H01L29/205H01L29/402
Inventor 黄火林孙仲豪
Owner DALIAN UNIV OF TECH
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