Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Structure of silicon-based metal intermediate layer compound semiconductor wafer and preparation method thereof

A compound and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc. Reliability and stability of devices and other issues to achieve the effect of reducing thermal stress, improving manufacturing process, and expanding application fields

Inactive Publication Date: 2020-01-31
BEIJING UNIV OF TECH
View PDF16 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the upper compound semiconductor wafer can be polished and flattened by chemical mechanical polishing (CMP:Chemical Mechanical Polishing), the thermal stress between the two wafers has not been released.
The existence of residual thermal stress will not only significantly affect the electrical and optical characteristics of the device on the silicon-based composite wafer (such as radiation recombination efficiency, luminous wavelength, etc.), but also affect the reliability and stability of the device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Structure of silicon-based metal intermediate layer compound semiconductor wafer and preparation method thereof
  • Structure of silicon-based metal intermediate layer compound semiconductor wafer and preparation method thereof
  • Structure of silicon-based metal intermediate layer compound semiconductor wafer and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

preparation example Construction

[0049] The invention provides a structure and preparation method of a silicon-based metal interlayer compound semiconductor wafer, which belongs to the field of semiconductor technology, and the structure comprises from top to bottom: a compound semiconductor wafer, a metal layer M 1 , metal layer M 2 and a silicon chip; the preparation method of the structure includes: using electron beam evaporation technology to vapor-deposit a metal layer on the compound semiconductor wafer and the silicon chip. Then use ion implantation and wafer bonding technology to realize silicon-based compound semiconductor wafer thin film. The introduction of the metal layer of the present invention can effectively alleviate the stress introduced by the difference in thermal expansion coefficient between the compound semiconductor wafer and the silicon chip; the present invention improves and improves the manufacturing process of semiconductor devices, and expands the application of wafer bonding te...

Embodiment 1

[0077] The invention provides a structure and a preparation method of a silicon-based metal alloy interlayer compound semiconductor wafer, comprising:

[0078] Step 1: Processing of the GaAs wafer, such as Figure 1-5 shown.

[0079] 1a. Select a gallium arsenide wafer 12, and perform PECVD on the upper surface of the gallium arsenide wafer 12. The deposited material is a silicon dioxide sacrificial layer 11, and the thickness of the silicon dioxide sacrificial layer 11 is 100 nm; figure 1 shown;

[0080] 1b. After the silicon dioxide sacrificial layer 11 is deposited, the gallium arsenide wafer 12 is implanted with ions through the silicon dioxide sacrificial layer 11, the implanted material is hydrogen ions, and the implanted dose is 1×1017 h + / cm 2 , the injected energy is 100keV; if figure 2 shown;

[0081] 1c. After the implantation is completed, the silicon dioxide sacrificial layer 11 on the gallium arsenide wafer 12 is completely removed by a CMP process, and th...

Embodiment 2

[0097] The invention provides a structure and a preparation method of a silicon-based metal alloy interlayer compound semiconductor wafer, comprising:

[0098] Step 1: Processing of the GaN wafer, such as Figures 9 to 13 shown.

[0099] 1a. Select a gallium nitride wafer 32, and perform PECVD on the upper surface of the gallium nitride wafer 32. The deposited material is a silicon nitride sacrificial layer 14, and the thickness of the silicon nitride sacrificial layer 14 is 200nm, such as Figure 8 shown;

[0100] 1b. After the silicon nitride sacrificial layer 14 is deposited, ion implantation is performed on the gallium nitride wafer 32 through the silicon nitride sacrificial layer 14. The implanted material is a mixture of hydrogen ions and helium ions, and the implantation dose of hydrogen ions is 2× 10 16 h + / cm 2 , the implantation energy is 120keV, and the implantation dose of helium ions is 7.5×10 15 he + / cm 2 , the injected energy is 150keV, such as Figur...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a structure of a silicon-based metal intermediate layer compound semiconductor wafer and a preparation method thereof. The structure sequentially comprises a compound semiconductor wafer, a metal layer M1, a metal layer M2 and a silicon wafer from top to bottom. The preparation method of the structure comprises the following steps: depositing a sacrificial layer on the compound semiconductor wafer; injecting ions into the compound semiconductor wafer through the sacrificial layer; polishing the sacrificial layer after the injection is completed and removing or partiallyremoving the sacrificial layer; evaporating the metal layer M1 on the compound semiconductor wafer or the remaining sacrificial layer on the compound semiconductor wafer; cleaning and drying the silicon wafer; evaporating the metal layer M2 on the silicon wafer; bonding the metal layer M1 on the compound semiconductor wafer and the metal layer M2 on the silicon wafer; and annealing the compositewafer after completion of bonding and stripping at the ion injection position to obtain the excess compound semiconductor wafer.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated devices, in particular to a structure and a preparation method of a silicon-based metal interlayer compound semiconductor wafer. Background technique [0002] In recent years, wafer bonding has been regarded as an important method for manufacturing micro-electro-mechanical systems (MEMS: micro-electro-mechanical systems) and heteroepitaxy, because it can manufacture silicon-on-insulator substrates (SOI: Silicon- on-insulator), and allows three-dimensional (3D) packaging of micro components. Wafer bonding allows polished semiconductor wafers to be bonded together without the use of organic binders. However, traditional high-temperature bonding (800-1000° C.) will generate thermal stress between materials due to different thermal expansion coefficients of different materials. As the temperature changes, the wafer bonding surface area will develop shear stress, peel stress and norm...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/482H01L21/60
CPCH01L23/4827H01L24/03H01L24/82H01L2224/0345H01L2224/82005
Inventor 王智勇黄瑞兰天
Owner BEIJING UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com