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Single electron memory having carbon nano tube structure and process for making it

A carbon nanotube, memory technology, applied in nanostructure manufacturing, nanotechnology for information processing, nanotechnology for materials and surface science, etc. Power consumption and other issues, to achieve the effect of reducing the preparation steps and avoiding the doping process

Inactive Publication Date: 2006-06-28
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, maintaining the trend of continuous scale reduction is facing an extremely serious challenge, that is, the capacitance in the storage unit cannot be too small. If the capacitance is too small to provide enough electrons to the amplifier, the entire memory will be flooded by noise, and the The reliability of information storage cannot be guaranteed; at the same time, the number of electrons in each storage unit will become smaller and smaller with the further improvement of the integration of storage devices, and the MOS field effect transistors in the memory will gradually become unstable.
[0003] In order to continue to maintain the high-speed development of memory devices, people hope to replace traditional memory devices with single-electron memory devices. Metal-oxide-semiconductor field-effect transistor (MOSFET) is used to prepare single-electron dynamic random access memory (J.Appl.Phys.2000, 12, 8594), although this device solves several problems such as power consumption that plague traditional memories, but This device uses the MTJ / MOSFET structure, which limits the further improvement of the integration level, because the size of the MOSFET cannot be too small, otherwise the number of working electrons is too small, which will affect the stability of the device
If the gate of the device is divided into three parts, and the split gate MOSFET is used to reduce the charge required for operation, the integration of the device is lower

Method used

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  • Single electron memory having carbon nano tube structure and process for making it
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  • Single electron memory having carbon nano tube structure and process for making it

Examples

Experimental program
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Effect test

Embodiment 1

[0046] according to figure 1 A single-electron memory having a carbon nanotube structure of the present invention was fabricated.

[0047] Choose (001) oriented silicon as the substrate 8, use the oxygen oxidation method, the oxidation temperature is 900°C, oxidize a 25 nm thick silicon dioxide insulating layer 7, and prepare a silicon dioxide insulating layer 7 by molecular beam epitaxy (MBE). A polysilicon layer with a thickness of 20 nanometers is heavily doped with arsenic to become an n-type semiconductor layer with a doping concentration of 5×10 13-2 .

[0048] In the prepared silicon layer, the electrode area 4, the data line pin 1, the control grid 2 of the nanowire and the nanowire 3 are prepared by using the electron beam photolithography method and the dry etching technology. The pin width of the data line is 80 nanometers; the size of the control gate of each nanowire is 80 nanometers wide and 80 nanometers long; the length of the nanowire is 120 nanometers long ...

Embodiment 2

[0051] according to figure 1 A single-electron memory having a carbon nanotube structure of the present invention was fabricated.

[0052] (001)-oriented silicon is selected as the substrate 8, and a silicon dioxide insulating layer 7 with a thickness of 25 nanometers is oxidized by using a dry oxygen oxidation method at an oxidation temperature of 900°C. A gold layer with a thickness of 30 nm was prepared by electron beam evaporation.

[0053] In the prepared gold layer, the electrode area 4, the data line pin 1, the control gate 2 of the nanowire and the nanowire 3 are prepared by electron beam photolithography and etching technology. The pin width of the data line is 90 nanometers; the size of the control gate of each nanowire is 100 nanometers wide and 100 nanometers long; the length of the nanowire is 160 nanometers long and 40 nanometers wide; wide; gold electrode 4, including two 30 nanometers thick, 50 nanometers wide, 50 nanometers long electrodes of carbon nanotube...

Embodiment 3

[0056] according to Figure 8 A single-electron memory having a carbon nanotube structure of the present invention was fabricated.

[0057] Choose (001) oriented silicon as substrate 8, use dry oxygen oxidation method, oxidation temperature is 900°C, oxidize a silicon dioxide insulating layer 7 with a thickness of 25 nanometers, and prepare a silicon dioxide insulating layer 7 by molecular beam epitaxy (MBE). A polysilicon layer with a thickness of 20 nanometers is heavily doped with arsenic to become an n-type semiconductor layer with a doping concentration of 6×10 13-2 .

[0058] In the prepared silicon layer, the data wire pin 1 , the control grid 2 of the nanowire and the nanowire 3 are prepared by using an electron beam photolithography method and a dry etching technology. The pin width of the data line is 80 nanometers; the size of the control gate of each nanowire is 80 nanometers wide and 80 nanometers long; the length of the nanowire is 110 nanometers long, 30 nanom...

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Abstract

The invention discloses a single electron dynamic random access memory (DRAM) device and process for making it. The device uses Si as substrate, there is a silicon oxide layer on the substrate, a nano line is made by etching processing in the metal or polysilicon layer on the silicon oxide insulation layer, one end of the nano line is data cable pin, there are two control grids parallel to the two sides of the namo lines at each side of them. The memory unit is the part of the namo line which is longer the the control grid and extending into between the two electrodes of the carbon nano transistor. By controlling several dozens or several electrons, the normal operation of the memory can be realized and without the influence of the random background charges, thus solving the problems such as stability, power consumption, radiation and grid leakage current faced in the development of the traditional memories, the invention also realizes the super-high density information storage under the low power consumption condition.

Description

technical field [0001] The invention belongs to memory devices, in particular to a single-electron memory designed and prepared using carbon nanotubes. Background technique [0002] Memory accounts for 40% of the world's semiconductor market. Semiconductor products other than memory are updated every 2 years, while memory is a generation every 18 months. Taking the development of dynamic memory (DRAM) as an example, in 1988 Japan The line width of the lines on the silicon chip reached 0.8 microns, and the 4Mb DRAM came out, thus entering the era of ultra-large-scale integration ULSI; in 1992, the 16Mb chip with a line width of 0.5 microns was put into production; in 1994, the 64Mb chip with a line width of 0.35 microns was launched. Chip production; 0.13-micron 4Gb DRAM will soon be realized. However, maintaining the trend of continuous scale reduction is facing an extremely serious challenge, that is, the capacitance in the storage unit cannot be too small. If the capacita...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/00H01L21/70B82B1/00B82B3/00
CPCB82Y30/00B82Y10/00
Inventor 孙劲鹏王太宏
Owner INST OF PHYSICS - CHINESE ACAD OF SCI
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