Thermal annealing for Cu seed layer enhancement

Abstract

Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seed layer by PVD, depositing a conformal seed layer enhancement film by electroplating, and then thermal annealing the seed layer enhancement film in an inert or reducing atmosphere to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.

Description

FIELD OF THE INVENTION[0001]The present invention relates to copper (Cu) and / or Cu alloy metallization in semiconductor devices, and to a method for manufacturing semiconductor devices with reliable, low resistance Cu or Cu alloy interconnects. The present invention is particularly applicable to manufacturing high speed integrated circuits having sub-micron design features and high conductivity interconnect structures.BACKGROUND ART[0002]The escalating demand for high density and performance impose severe requirements on semiconductor fabrication technology, particularly interconnection technology in terms of providing reliable low RxC (resistance x capacitance) interconnect patterns with higher electromigration resistance, wherein sub-micron vias, contacts and trenches have high aspect ratios.[0003]Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conducti...

AI Technical Summary

Benefits of technology

The present invention provides a method for manufacturing a semiconductor device with reliable, low resistance copper or copper alloy interconnects and significantly reduced voids. The method involves depositing a barrier layer, a seed layer, and a conformal seed layer enhancement film in an opening in a dielectric layer, followed by thermal annealing and filling the opening with copper or a copper alloy. The method can be used to form a dual damascene opening in dielectric material, and the resulting copper or copper alloy lines have low resistivity and are in communication with an underlying copper or copper alloy via. The method can also be carried out with other embodiments and modifications.

Problems solved by technology

The escalating demand for high density and performance impose severe requirements on semiconductor fabrication technology, particularly interconnection technology in terms of providing reliable low RxC (resistance x capacitance) interconnect patterns with higher electromigration resistance, wherein sub-micron vias, contacts and trenches have high aspect ratios.

As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RxC delay caused by the interconnect wiring increases.

As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs.

In implementing Cu metallization, particularly in damascene techniques wherein an opening is formed in a dielectric layer, particularly a dielectric layer having a low dielectric constant, e.g., a dielectric constant less than about 3.9, various reliability, electromigration and resistance issues are generated.

Reliability issues stem, in part, from the difficulty in forming a continuous seed layer on a barrier layer in an opening, particularly as the feature sizes continue to shrink into the deep sub-micron regime.

As a result of reduced feature sizes and high aspect ratios, it is extremely difficult to deposit a continuous seed layer lining the sidewalls of the opening.

In addition, it is even difficult to effectively plate the seed layer 12 on the bottom of the opening.

Consequently, voids are induced leading to high resistance vias and lines or open circuits.

However, it was found that such seed layer enhancement films exhibit poor properties, such as an undesirable surface roughness, e.g., an average surface roughness (Ra) greater than 25 Å vis-à-vis an Ra of 5 Å to 7 Å for a conventionally deposited PVD Cu film.

It was also found that such a seed layer enhancement film 20 not only exhibits an undesirable surface roughness but also undesirably high impurity concentrations of elements such as carbon, oxygen, nitrogen and hydrogen.

As a result, the subsequently deposited electroplated Cu film exhibits high resistivity, high surface roughness and voids, leading to significantly increased via / line resistance and lower circuit speed, in addition to generating electromigration and other reliability issues.

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