High depth width ratio TSV through hole step-by-step etching and side wall modification method

Abstract

The invention discloses a high depth width ratio TSV through hole step-by-step etching and side wall modification method. The method comprises the steps that a layer of SiO2 is deposited on the surface of a P (100) type single crystal silicon wafer by using a PE CVD method; photoresist is coated on the surface of the SiO2; exposing and developing are carried out; a silicon dioxide window needing etching is exposed; a plasma dry etching method is used to carry out the etching of a silicon dioxide layer on the exposed window, and etching is carried out until the surface of the single crystal silicon wafer; and an optimized multiple-step Bosch etching process is carried out. According to the invention, K+ pollution is not introduced; high temperature process processing is avoided; the size of a through hole occupies a small chip area; the economic benefit is high; the method is compatible with an IC technology; the through hole of high density and high depth width ratio can be produced; the 'scallop' size of a side wall of the through hole can be reduced; the roughness of the side wall is improved; the difficulty of a subsequent side wall insulation process is reduced; the breakdown voltage can be enhanced; and the reliability of a TSV three-dimensional integrated device is improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics. Background technique [0002] At present, the commonly used TSV through-hole manufacturing technology mainly adopts the ICP etching technology Bosch process to realize the manufacture of large aspect ratio TSV through-holes. The "U.S. Patent No. 5501893" patent states that the Bosch process uses passivation and etching alternately for deep hole etching. First deposit a layer of polymer with C4F8 for sidewall protection, and then use SF6 to etch away the polymer and silicon at the same time. The passivation and etching steps are alternately cycled at high speed, and anisotropic etching effect is finally achieved. But the disadvantage of this method is: the SF6 used in the traditional Bosch process has isotropic etching characteristics, so the sidewall will be etched laterally during the etching process, thereby forming a micro-curved structure. After several subsequent cycles of passiv...

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Problems solved by technology

But the disadvantage of this method is: the SF6 used in the traditional Bosch process has isotropic etching characteristics, so the sidewall will be etched laterally during the etching process, thus forming a micro-curved structure

However, there are two main problems in this method: first, due to the existence of the inherent angle between the (111) crystal plane and the (100) crystal plane, the opening of the TSV via hole will increase with the increase of the etching depth, making this type of TSV via hole The occupied area is too large and the economy is poor; the second is that the process uses KOH as the auxiliary liquid to easily introduce K+ pollution, which will cause K+ pollution to the CMOS process line

However, the disadvantages of this method are: first, it takes a long time for a high-temperature process, and cannot be used for the Via-last TSV process after the metallization process is completed; second, for SOI materials, HF acid is used to oxidize the side wall of TSV " When the scallop structure is used, the buried oxide layer will be corroded at the same time, causing the TSV via structure to form a cavity structure between the top silicon and the silicon substrate, and the subsequent insulating layer, barrier layer, and seed layer are easy to break here, forming hidden dangers. Based on SOI materials This method cannot be used for devices; third, for TSV through holes with small apertures, due to the liquid surface tension effect, HF acid cannot enter the through holes as deep as tens of microns, and the step of removing the oxide layer is difficult to achieve

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