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Self-aligning interconnection method used for manufacturing high density MRAM

A self-alignment, high-density technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problem of difficulty in contacting MTJ components with the upper conductive layer, and reduce production costs and risks. The effect of increasing yield

Active Publication Date: 2018-08-07
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to provide a self-aligned interconnection method for manufacturing high-density MRAM, to solve the problem that the MTJ element and the upper conductive layer are difficult to form contact with in the prior art when manufacturing high-density MRAM

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  • Self-aligning interconnection method used for manufacturing high density MRAM
  • Self-aligning interconnection method used for manufacturing high density MRAM
  • Self-aligning interconnection method used for manufacturing high density MRAM

Examples

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Embodiment 1

[0045] With reference to the accompanying drawings, Figure 1-6 The exemplary diagram shows a method for making contact with the upper conductive layer by MTJ elements of an array of MTJ elements in an MRAM device according to the present invention. figure 1 is a cross-sectional view of an MTJ element array thin film formed on the dielectric region 10 . The dielectric region 10 may be composed of any suitable dielectric material such as silicon dioxide (SiO2), aluminum oxide (Al2O3). The contact hole 12 may comprise any suitable conductive material such as aluminum (Al), aluminum alloy, copper (Cu), copper alloy, tungsten (W), titanium (Ti), tantalum (Ta), and may contain such as nitrogen Barrier materials such as tantalum oxide (TaN), titanium nitride (TiN), or titanium tungsten (TiW). Only the contact hole 12 is marked in the figure, and there are multiple layers of Metal and contact holes below the contact hole 12, as well as the bottom transistor; although not marked, t...

Embodiment 2

[0053] refer to Figure 7 , in the second embodiment of the present invention, the cylindrical MTJ element 16 is located directly above the contact hole 12, and the corresponding applications may include spin-transfer torque (STT), thermal-assist (Thermal-assist), voltage regulation (VCMA), etc. The MTJ element needs to be placed on the element structure directly above the contact hole to reduce the unit area to realize a high-density MRAM device; Etching is stopped above the dielectric region 10, which also includes appropriate operations such as sidewall cleaning, damaged layer removal, and structural restoration after the columnar MTJ element is patterned to obtain the best MTJ element performance; refer to Figure 7 It also includes the step of in-situ depositing the first dielectric protection layer 20 after the columnar MTJ element is patterned. This step preferably adopts plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), electron beam e...

Embodiment 3

[0057] refer to Figure 10-12 The example diagram shows a method for realizing the electrical contact between the MTJ element in the MRAM device and the third contact hole 32 through the upper conductive layer according to the present invention. Although not shown, the third contact hole 32 is typically interconnected with, for example, a silicon-based semiconductor transistor through a contact hole or a metal conductive stack. These transistors make up the control and readout circuitry of the MRAM. refer to Figure 11 , in this embodiment, after the second dielectric protection layer 22 is formed to be flattened and the first dielectric protection layer 20 is at least partially exposed, a third mask 34 is formed over the third contact hole 32 using standard patterning techniques , the third mask can be formed by using a suitable photolithography process such as deep ultraviolet exposure (DUV) and a suitable etching process such as reactive ion etching (RIE), inductively cou...

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Abstract

The invention relates to a self-aligning interconnection method used for manufacturing a high density MRAM; the method comprises the following steps: 1, depositing a bottom conductive electrode layer,a MTJ element layer and a metal mask layer; 2, preparing cylindrical MTJ elements, and in situ depositing a first dielectric protective layer used for protecting the cylindrical MTJ elements; 3, making a bottom conductive electrode, and depositing a second dielectric protective layer used for filling gaps of a cylindrical MTJ element array; 4, leveling the second dielectric protective layer, andexposing the first dielectric protective layer above the cylindrical MTJ elements; 5, etching the first and second dielectric protective layers in the same time, exposing the metal mask layer above the cylindrical MTJ elements, and forming second contact holes above the cylindrical MTJ elements in a self-aligned manner; 6, depositing an upper conductive layer. The method can greatly increase the MRAM device yield rate, can save a lithography step, and can greatly reduce the production costs and risks.

Description

technical field [0001] The invention relates to a self-aligned interconnection method for manufacturing high-density MRAM, which relates to the technical field of magnetic random access memory (MRAM) or magnetic sensor, etc., involving magnetic tunnel junction (MTJ) spin device manufacturing technology, and in particular to a A method for making an electrical contact between an MTJ element in a high-density MRAM and an upper conductive layer. Background technique [0002] Magnetic Random Access Memory (MRAM) is a non-volatile memory with many advantages such as high-speed reading and writing, non-volatility, low power consumption, reliability, radiation resistance, and nearly infinite repeated erasing times. Volatile memory technology, which provides advantages over traditional memories such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM) and flash memory in many applications, and thus has a promising application prospect. [0003] The core storag...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/22H01L21/768
CPCH01L21/76897H10B61/10
Inventor 曹凯华赵巍胜崔虎山赵超
Owner BEIHANG UNIV