A micron-scale single crystal copper interconnect structure and preparation method thereof

Abstract

The invention discloses a micron-level single crystal copper interconnection structure and a preparation method thereof, belonging to the field of electronic packaging. The structure mainly includes a substrate, a barrier layer, a phosphorus-containing copper seed layer, and a copper needle; the substrate is a dielectric layer with through holes and grooves, a silicon wafer with blind holes, and a semiconductor substrate with copper pillar windows. A kind of; the barrier layer is arranged on the inner sidewall and bottom of the through hole and the trench of the dielectric layer, the inner sidewall and bottom of the blind hole of the silicon wafer, or the bottom of the copper column window on the semiconductor substrate; A phosphorous copper seed layer is disposed over the barrier layer parallel to the substrate; the copper needles are deposited on the phosphorous copper seed layer. In the structure, phosphorus element is doped into the copper seed layer, and the micron-scale single crystal copper needle can be formed as a copper interconnection structure without the assistance of additives during electroplating. The copper interconnection structure obtained by the invention is a complete single crystal structure, and there is no lateral grain boundary, so that the transmission performance of the copper interconnection is significantly improved.

Description

technical field [0001] The invention relates to the technical field of copper interconnection in electronic packaging, in particular to a micron-scale single crystal copper interconnection structure and a preparation method thereof. A micron-scale single crystal copper interconnect structure is prepared on the seed layer. The method can be applied to Damascus technology, TSV (through silicon via) technology, copper pillar bump technology, etc. in three-dimensional system-in-package. Background technique [0002] In deep submicron integrated circuits, three-dimensional system-in-package can effectively utilize the three-dimensional space, improve the packaging density, reduce the package volume, shorten the lead length, and improve the transmission speed. Among them, Damascus technology for interconnection between chips, TSV technology for interconnection between silicon wafers, copper pillar bump technology for interconnection between chips and substrates, etc., have become...

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Problems solved by technology

[0005] In the existing research, there are attempts to increase the grain size, thereby reducing the number of grain boundaries to improve electrical conductivity, basically using the method of thermal annealing after electroplating, which can reduce the resistivity by about 8%, but these studies have not The influence of grain boundaries on electrical conductivity cannot be completely eliminated, and the electroplating process has not been improved. The help of additives is still needed, but the step of thermal annealing after electroplating is increased.

There are also researches that use electroless plating or electroplating to directly obtain nano-single crystal copper cones, but the electroless plating method has low repeatability and is not compatible with the preparation process of copper interconnection structures. The key to obtaining single crystal copper cones by electroplating is additives, and nanoscale is not suitable for copper interconnect structures

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