Capacitance with combined type storage section structure and its manufacturing method
A storage node, composite technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as unspecified, reduce diffusion, increase manufacturing costs, etc., to reduce deposition process temperature, improve dielectric layers Features, the effect of omitting production costs
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Embodiment 1
[0048] Figure 4-1 to Figure 4-5 , is the manufacturing method of the capacitor with the recessed composite storage node structure according to Embodiment 1 of the present invention. like Pic 4-1 As shown, a second insulating layer 26 and a third insulating layer 28 are sequentially formed on the surface of the semiconductor substrate 20, wherein the second insulating layer 26 is used as an etching stop layer, and silicon nitride or silicon oxynitride materials can be used. , the thickness is about 10-100 nm; the third insulating layer 28 can be made of silicon oxide material, and the thickness is about 300-800 nm. Then, if Figure 4-2 As shown, the predetermined patterns of the third insulating layer 28 and the second insulating layer 26 are etched and removed by lithography and etching processes until the surface of the polysilicon plug 24 is exposed to define a plurality of trenches 30 . Wherein, the diameter range of each groove 30 may be 0.1-0.18 μm or 0.2-0.45 μm, an...
Embodiment 2
[0052] Figure 5-1 to Figure 5-5 , is the manufacturing method of the capacitor with the pedestal composite storage node structure according to the second embodiment of the present invention. like Figure 5-1 As shown, a second insulating layer 24 is sequentially formed on the surface of the semiconductor substrate 20, which can be made of silicon nitride or silicon oxynitride, with a thickness of about 10-100 nm. Then, the predetermined pattern of the second insulating layer 26 is etched away by using lithography and etching processes until the surface of the polysilicon plug 24 is exposed, so as to define and form several shallow trenches 30'. Next, if Figure 5-2 As shown, a Ru metal layer 32 is first deposited on the surface of the semiconductor substrate 20 with a thickness of about 300-800 nm to cover each trench 30', and then the Ru metal layer 32 with a predetermined pattern is removed by lithography and etching processes. , to form a stud-like Ru metal layer 32 on ...
Embodiment 3
[0055] In order to effectively prevent oxygen diffusion and polysilicon diffusion between the composite storage junction and the polysilicon plug 24, in Embodiment 3 of the present invention, a barrier layer 40 is provided between the composite storage junction and the polysilicon plug 24, and its material can be TiN , TiAlN, TiSiN, TaSiN and other barrier materials. like Figure 6-1 As shown, it is a schematic diagram of setting a barrier layer 40 between the recessed composite storage node and the polysilicon plug 24 in Embodiment 1 of the present invention; Figure 6-2 As shown, it is a schematic diagram of setting a barrier layer 40 between the pillar type composite storage node and the polysilicon plug 24 according to Embodiment 2 of the present invention.
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Abstract
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