Method and device for rapidly filling vertical TSV hole with liquid alloy

Abstract

The invention provides a method and device for rapidly filling a vertical TSV hole with liquid alloy, and relates to the field of microelectronic packaging. With solder alloy as a filling material, asilicon dioxide insulation layer is deposited on the surface of a TSV silicon wafer and in a blind hole in advance through chemical vapor deposition, a titanium barrier layer is deposited on the wallof the hole through physical vapor deposition, and finally, a copper layer is electroplated on the surface of the silicon wafer deposited with silicon dioxide to serve as a wet layer; and the obtainedwafer is placed in a vacuum chamber, the alloy is heated to be molten, the silicon wafer is pressurized when completely making contact with the molten alloy due to the wettability of the solder alloyand copper, the pressure in the vacuum chamber is maintained after pressurization, and filling is completed after the temperature is decreased. By the adoption of the method and device, the filling efficiency of the TSV hole can be improved, and imporous filling of a high-depth-wide-ratio TSV blind hole with the solder alloy is completed. The alloy and the wall of the TSV hole are firmly bonded together, and the filling process is simple. The TSV hole filling device comprises a vacuum outlet, a nitrogen inlet, a pressure gauge, a reaction chamber, a heating device and a temperature display device, wherein the vacuum outlet and the nitrogen inlet are controlled through valves.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging, in particular to a method and a device for rapidly filling a through-silicon hole with an alloy. Background technique [0002] Moore's law has been guiding the development direction of electronic information technology since 1965. However, with the emergence of smaller line width technology, people realize that it is becoming more and more important to integrate higher density circuits and realize more functions on a single chip. Difficulties, three-dimensional integrated packaging technology is considered to be the preferred solution to achieve device miniaturization and multi-function, and through silicon via (Through Silicon Via, TSV) technology is the core of three-dimensional integrated packaging technology, TSV technology can realize the interconnection between stacked chips Vertically interconnected up and down, this structure can play the role of signal conduction and he...

AI Technical Summary

Problems solved by technology

Due to its high aspect ratio structure, the copper electroplating process generally takes several hours to tens of hours, the filling efficiency is low, and the electrolyte and additives are toxic and pollute the environment

[0004] There is an urgent need for a new filling method to solve this problem. At present, most of them change the electroplating process parameters to reduce the defects in the filling process, but the problems of long time consumption and high production cost have not been solved.

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