2results about How to "Guaranteed storage efficiency" patented technology

This invention belongs to the field of integrated circuit design technology, specifically relating to a method for optimizing integrated circuit design data. This method first constructs a "tool-layer-semantic" data acquisition architecture, integrating multi-channel parallel acquisition units to collect heterogeneous data from multiple sources. Compliance pre-verification is performed through hardware logic circuits and a verification rule base, extracting key data identifiers. A three-level incremental compression strategy based on key data priority, combined with an intelligent index integrating multi-dimensional indexes, is used for compression and storage. The stored data undergoes multi-dimensional optimization, including semantic deduplication, priority optimization, format conversion, and source quality backtracking, forming a unified format optimized semantic. Through an interactive interface, it is adapted and interacted with electronic design automation tools. After consistency verification and performance testing feedback loops, the final design data and full-process traceability information are obtained and stored. This invention achieves unified management, efficient compression, intelligent optimization, and full-process traceability of design data.

Embodiments of the present disclosure provide an indirect memory copy method, a processing unit, a computing device and a system. The processing unit of the embodiments of the present disclosure comprises an operation unit, an addressing unit and an index cache, and the addressing unit and the index cache are located between the main storage area outside the processing unit and the operation unit. The operation unit executes an indirect memory copy instruction, and the indirect memory copy instruction at least has a base address, an index address and a destination address, so as to send the index address to the index cache and send the base address and the destination address to the addressing unit; the index cache loads a corresponding index from the main storage area according to the index address and sends the index to the addressing unit; the addressing unit determines a source address of the main storage area corresponding to source data according to the base address and the index; and the addressing unit loads the source data from the main storage area according to the source address and sends the source data to the destination address of the internal cache of the operation unit. The scheme of the embodiments of the present disclosure saves the computing resources of the operation unit itself.