Preparation technology of multi-purpose silicon micro-nano structure

Abstract

The invention relates to a preparation technology of a multi-purpose silicon micro-nano structure, and belongs to the preparation technology field of new materials. A preparation method of a large-area highly-orderly silicon micro-nano structure array is researched though the combination of the metal-catalyzed silicon corrosion technology and the photoetching technology. A micro structure image on a photoetching mask plate is accurately copied to the surface of a clean silicon chip coated with a photoresist by utilizing an electron beam or ultraviolet light and other exposure technologies so as to obtain the image required during the corrosion process and protected by etching resist. A metal silver film is deposited on the surface of the silicon chip after the surface of the silicon chip is processed by utilizing high-vacuum heat-evaporation and other technologies; after the etching resist coated on the surface of the silicon chip and the silver film coated on the resist are removed, the silicon chip is immerged into a closed container of hydrofluoric acid corrosion solution containing an oxidant and processed for 10 to 100 minutes so as to obtain the large-area highly-orderly silicon micro-nano structure array. The large-area highly-orderly silica micro-nano structure array has wide application prospect in the fields of solar batteries, lithium battery cathode materials, gas sensors, active surface reinforced Raman spectrometry substrate and the like.

Description

technical field [0001] The invention relates to a multi-purpose ordered silicon micro-nano structure preparation technology, which belongs to the field of new material technology and nanometer materials. Background technique [0002] Due to their unique structure and physical properties, semiconductor micro-nanostructure materials have broad application prospects in nano-optoelectronics and new solar cell devices. Due to the important position of silicon materials in the traditional microelectronics industry, the research of one-dimensional silicon nanowires has received great attention. The current nano-silicon wire preparation methods mainly include chemical vapor deposition and oxide-assisted growth techniques. Due to the limitations of the growth mechanism, these methods usually require relatively high temperatures and some complicated equipment, resulting in high production costs. For example, the silicon wire growth temperature in patent 00117242.5 is as high as 1600...

AI Technical Summary

Problems solved by technology

Although this technique can be applied to silicon substrates with different doping types, concentrations and orientations, and can control the length and crystallographic orientation of nanowires, it is difficult to obtain silicon nanowires with uniform diameter and orderly arrangement.

Our research group recently used polystyrene nanosphere and silica nanosphere template technology to prepare silicon nanowires with uniform diameter and order [Kuiqing Peng, Mingliang Zhang, Aijiang Lu, NingBew Wong, Ruiqin Zhang, Shuit-Tong Lee .Ordered Si nanowire arrays via NanosphereLithography and Metal-induced etching.Applied Physics Letters 2007, 90, 163123], but the use of polystyrene nanosphere technology to prepare silicon nanowires requires reactive ion etching (RIE), resulting in silicon nanostructures The preparation efficiency is seriously reduced and the cost is greatly increased

At the same time, it is difficult for these two technologies to realize the preparation of large-area silicon micro-nanostructures.

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