31results about How to "Low latency processing" patented technology

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel filter is used at the receiver. Also, disclosed are techniques for selecting codes to use for the controllable delays as well as techniques for identifying and tracking interfering ladar pulses and their corresponding delay codes. The use of a ladar system with pulse deconfliction is also disclosed as part of an optical data communication system.

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel filter is used at the receiver. Also, disclosed are techniques for selecting codes to use for the controllable delays as well as techniques for identifying and tracking interfering ladar pulses and their corresponding delay codes. The use of a ladar system with pulse deconfliction is also disclosed as part of an optical data communication system.

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel filter is used at the receiver. Also, disclosed are techniques for selecting codes to use for the controllable delays as well as techniques for identifying and tracking interfering ladar pulses and their corresponding delay codes. The use of a ladar system with pulse deconfliction is also disclosed as part of an optical data communication system.

Disclosed herein are a number of example embodiments that employ controllable delays between successive ladar pulses in order to discriminate between “own” ladar pulse reflections and “interfering” ladar pulses reflections by a receiver. Example embodiments include designs where a sparse delay sum circuit is used at the receiver and where a funnel filter is used at the receiver. Also, disclosed are techniques for selecting codes to use for the controllable delays as well as techniques for identifying and tracking interfering ladar pulses and their corresponding delay codes. The use of a ladar system with pulse deconfliction is also disclosed as part of an optical data communication system.

The disclosed embodiments relate to implementation of a trading system, which may also be referred to as a trading system architecture, having improved performance which further assures transactional determinism under increasing processing transaction loads while providing improved trading opportunities, fault tolerance, low latency processing, high volume capacity, risk mitigation and market protections with minimal impact, as well as improved and equitable access to information and opportunities.

The disclosed embodiments relate to implementation of a trading system, which may also be referred to as a trading system architecture, having improved performance which further assures transactional determinism under increasing processing transaction loads while providing improved trading opportunities, fault tolerance, low latency processing, high volume capacity, risk mitigation and market protections with minimal impact, as well as improved and equitable access to information and opportunities.

An architecture for a specialized electronic computer for high-speed data lookup employs a set of tiles each with independent logic elements lookup memory portions. The tiles may each comprise gate-array-like functional units that may be wired together by a multi-way switch for extremely low latency.

The invention discloses a railway crossing remote centralized control and intelligent early warning integrated system. The system comprises a dispatching center control subsystem, a dispatching center video/audio subsystem, a crossing field front-end device subsystem and an optical fiber communication subsystem. The dispatching center video/audio subsystem is connected with the dispatching center control subsystem. The crossing field front-end device subsystem is connected with the dispatching center control subsystem through the optical fiber communication subsystem. The dispatching center control subsystem comprises a control server and a communication controller, achieves monitoring and control over all devices of the other three subsystems and completes remote control command for dispatching operators. The dispatching center video/audio subsystem comprises a video image display module and a video/audio storage device matrix. Remote videos, remotes audios and remote control are centralized and integrated into the system, the efficiency is improved, the operation is facilitated, and the system is safer and more reliable.

In an encryption apparatus, a division part determines as a unit of processing, the number of blocks to be encrypted using the same key, and divides plaintext data input from a second input part by the unit of processing. An encryption part generates from a common key input from a first input part, processing keys 1 to N which are different from each other and the number of which is the same as the number N of divisions of the plaintext data at the division part, and generates encrypted data by encrypting for each unit of processing determined by the division part, individual blocks of the plaintext data input from the second input part, by means of a block cipher F using the same generated processing key I.

The invention discloses a robot chassis control system and method based on time hard synchronization, and the system and method carry all sensors based on a high-speed processing SOC chip with an embedded FPGA + ARM core, and achieve the algorithm of the whole chassis control system. Compared with an FPGA + ARM heterogeneous separation scheme, the integration level and the communication interconnection rate of the system can be further improved. Data requests and responses of all sensors can be processed in real time by means of the efficient and powerful parallel processing capacity of the FPGA; meanwhile, a global clock module is constructed in the FPGA, and the FPGA automatically marks timestamps according to the clock module when processing the sensor data, assembles all the sensor data into frames and sends the frames to the ARM core. The ARM is responsible for logic protocol analysis and control process scheduling, plays a connection link role, and performs encapsulation and uploading of a lower computer network communication protocol and analysis and task scheduling of an instruction issued by an upper computer. The method ensures that the robot chassis control system can effectively solve the problem of data transmission delay, and has a good application prospect.

The invention provides a low-delay VDE satellite-borne downlink digital signal processing system based on an FPGA, and the system is characterized in that the system comprises a data partitioning andhigh-speed forwarding module, an efficient partitioning Turbo coding and scrambling processing module, and a multi-bandwidth universal modulation transmission processing module. According to the low-delay digital signal processing method and module design based on the VDE communication protocol mechanism, VDE modulation signal sending delay is greatly reduced, FPGA resource occupation is reduced,and the low-delay digital signal processing method and module design can be applied to a VDE satellite-borne downlink digital signal processing scene.