This invention discloses a simplified
dataflow instruction set processor, comprising on-
chip memory, a planar arithmetic unit, a cube arithmetic unit, a point arithmetic unit, a
tensor arithmetic unit, and an instruction controller. The on-
chip memory directly reads and stores computational data from off-
chip memory, and this computational data is used for computation by the planar arithmetic unit, the cube arithmetic unit, and the point arithmetic unit. The
tensor arithmetic unit directly obtains data from off-chip memory and performs swapping, splitting, aggregation, and reverse aggregation operations on the
tensor data according to instruction configuration information from the instruction controller. The instruction controller directly obtains instructions from off-chip memory and sends instruction configuration information to the planar arithmetic unit, the cube arithmetic unit, the point arithmetic unit, or the tensor arithmetic unit according to the instructions. This processor features simplified and limited computational types, maintaining the high efficiency of a
dataflow computing architecture while possessing general computing characteristics, thus achieving the advantages of high computing power, high
clock speed, and low
power consumption.