The application discloses a high-
concurrency processor architecture based on an instruction-level
event structure and a scheduling method thereof, is based on RISC-V instructions, and defines the stagnation, successful termination, sequential execution, conditional branching and merging operation of a program through a process algebra (PA-ISA) oriented to an
instruction set architecture (ISA). On the basis of the PA-ISA, the dependence relationship between instructions in program execution is described through an instruction-level
event structure (IES). The instruction-level
event structure model is adopted to describe the dependence relationship between instructions in the program, the instruction
concurrency is improved, and good expansibility is achieved. The high-
concurrency processor architecture based on the IES is combined with an
asynchronous circuit, an event triggering is taken as a basic execution advancing mode, the frequency or energy efficiency is improved, the bypass control mechanism in the out-of-order execution is simplified, and the
system reliability is improved. The instruction-level event structure is combined with a double-path instruction fetching mechanism, the instruction waste and performance loss are reduced, and the
fault tolerance capability under a large-scale instruction fetching strategy is optimized.