110 results about "Variable frame rate" patented technology

An image rendering unit (IRU) of a device determines the dynamic frame rate capabilities (DFRCs) of a display and an image frame rate of content to be displayed. Preferably, the DFRCs are stored in a storage device deployed within the display itself. Based on the DFRCs and the image frame rate for the content, the IRU determines an updated frame rate and thereafter provides the content to the display at the updated frame rate. Where control of power consumption is desired, selection of a reduced frame rate can effect a power savings. In this manner, the present invention provides flexible control over display frame rates and/or power consumption of the device.

The present invention relates to a method for driving a solid-state image pickup device and a camera provided with the driving function. In the method for driving the solid-state image pickup device and the camera according to the present invention, the frame rate of the image pickup device is varied according to the frequency of illumination or the brightness. Alternatively, the frame rate of the image pickup device is varied and an electronic shutter is driven at the same time according to the brightness. Consequently, it is possible to suppress occurrence of flicker and give a liberal brightness condition under which an image can be picked up.

A digital camera capable of variably setting a frame rate may include an imaging device which outputs a plurality of temporally continuous image frames when photographing a moving image. The digital camera may also include a digital signal processor that determines a frame rate with which the image frames are filed, wherein the digital signal processor variably determines the frame rate according to a motion speed of a subject in the frames. The digital camera may further include a recording medium in which the filed image frames are stored. Accordingly, as the frame rate is varied according to the motion of a subject, the motion of the subject can be smoothly realized in a high motion speed section from a reproduction perspective, and substantially repeated image frames can be removed in a low speed motion section. Thus, the size of moving image files can be reduced, saving memory resources.

When a recording start executed in a variable-speed recording mode, at ST44 a signal having a variable frame rate is selected on the basis of a validity signal from among image signals having a predetermined output frame rate in which the images having the variable frame rate are contained and stored in a memory. If it is decided at ST46 that a phase difference between a write position and a read position in the memory has reached a recording start level, the stored signal is recorded in a recording medium at ST47. If it is decided at ST48 that the phase difference has decreased to a recording stop level, recording to the recording medium is stopped at ST49. When an end operation is executed at ST51, the signal in the memory is recorded in the recording medium to then end actions. The signals are selected and recorded, thus resulting in a smaller signal quantity. Further, if the variable frame rate is varied, video effects can be confirmed only by reproducing the recorded signals.

The invention provides a video frame rate up-conversion method and system based on a convolutional neural network. The method includes: receiving an initial video transmitted by a sending end; dividing the initial video into multiple image blocks of which each comprises two consecutive frame images; using the two consecutive frame images in the image block as input of the target convolutional-neural-network, and synthesizing an intermediate frame corresponding to the two consecutive frame images, wherein the target convolutional-neural-network is obtained through training of a preset trainingdata set, and includes an encoder, a decoder and an optical-flow prediction layer; and inserting the intermediate frame image into the image block to obtain a target video after video frame rate up-conversion. Therefore, mapping from a previous frame and a next frame to the intermediate frame can be completed, a frame rate of the original video is improved, and up-conversion of the video frame rate is better completed.

An image signal processing device that includes: a recording section; a first processing section that calculates an amount of screen motion through detection of a motion of a captured image, and determines a frame rate through comparison between the amount of screen motion and a preset motion threshold value; and a second processing section that performs recording of the captured image to the recording section using the dynamically-variable frame rate notified by the first processing section.

A motion picture camera arrangement comprises a motion picture camera and a display device, wherein the motion picture camera has an image sensor for taking images at a variable frame rate and wherein the display device displays the taken images at a settable display rate. A method of operating the motion picture camera arrangement comprises the steps of: selecting a frame rate; determining a setting value for the display rate of the display device, wherein the setting value corresponds, in dependence on the selected frame rate, either to the selected frame rate or to a product or quotient of the selected frame rate and a whole-number multiplier or divisor; operating the image sensor at the selected frame rate; and operating the display device using the determined setting value for the display rate.

Methods, systems, and apparatuses for performing rate control for encoding of video frames are provided. A first timestamp is received that indicates a capture time for a prior video frame. A second timestamp is received that indicates a capture time for a current video frame. A time difference between the second timestamp and the first timestamp is determined. An average video data bit encoding rate is multiplied by the determined time difference to calculate a bit budget. An indication of a number of video data bits that have been encoded is received. The number includes a number of encoded video data bits of the prior video frame and of any further video frames encoded subsequent to the prior video frame and prior to the current video frame. A virtual buffer fill level is adjusted based on a difference between the indicated number of video bits that have been encoded and the calculated bit budget. A quantizer parameter is adjusted based on the adjusted virtual buffer fill level. The current video frame is encoded according to the adjusted quantizer parameter.

The invention provides a video frame rate upconversion method and a video frame rate upconversion system based on a cyclic convolution neural network. Dividing the initial video into groups of image blocks comprising two consecutive frames of images; taking two consecutive frames of images in the image block as inputs of a target cyclic convolution neural network, and synthesizing intermediate frame images corresponding to the two consecutive frames of images; wherein, the target cyclic convolution neural network is trained by a preset training data set. The intermediate frame image is inserted into the image block to obtain the target video after the video frame rate upconversion. Thus, the mapping from the front and back two frames to the middle frame can be completed, the frame rate ofthe original video is improved, and the up-conversion of the video frame rate is better completed.

An image signal generation portion 10 generates an image signal DVb of a variable frame-rate picked-up image whose frame rate can be varied. A frame rate conversion portion 30 converts a frame rate of an image signal DVu supplied to it into a frame rate of the image signal DVb and synchronizes them to provide an image signal DVw. A monitor image signal generation portion 40 uses the image signals DVb and DVw to generate an image signal DVmix of an image in which an image based on the image signal DVb and an image based on the image signal DVw are mixed and output it as a monitor image signal DMTout or SMTout. Alternatively, it generates an image signal DVwp of an image in which a part of an image based on the image signal DVb is replaced by an image based on the image signal DVw and outputs it as the monitor image signal DMTout or SMTout. It is possible to simultaneously display a variable frame-rate picked-up image and an image having a different frame rate.

A video recording apparatus provides a slow motion effect or a quick motion effect by digitally converting the frame-rate instead of by changing the playback speed of the film, and using few recording media without requiring any special device at playing. A picture encoding part encodes only valid frames by changing a rate-controlling method so that a predetermined playing frame-rate is obtained at a standard data-rate at playing. And a TS multiplexing part multiplexes by converting a frequency of a standard STC clock by only a ratio of valid frame-rate and playing frame-rate, and generating values for PCR, PTS, and DTS.

A video processing apparatus and a video processing method are used to capture a view region as a video result. The video processing apparatus includes a video sensor, a temporary memory, and a video pipeline. The video sensor captures the view region at a sensor frame rate and generates a video having a plurality of frames. The video pipeline receives one of the frames directly from the video sensor to serve as a first frame. The video pipeline processes the first frame to generate a temporary result frame, and then generates a video result at a video frame rate according to the temporary result frame and a second frame directly received from the video sensor, wherein the video frame rate is smaller than the sensor frame rate. The video processing method captures the view region as the video result by using the video processing apparatus.

Systems, apparatuses, and methods for encoding bitstreams of uniquely rendered video frames with variable frame rates are disclosed. A rendering unit and an encoder in a server are coupled via a network to a client with a decoder. The rendering unit dynamically adjusts the frame rate of uniquely rendered frames. Depending on the embodiment, the rendering unit conveys a constant frame rate to the encoder by repeating some frames or the rendering unit conveys a variable frame rate to the encoder by conveying only uniquely rendered frames to the encoder. Depending on the embodiment, the encoder conveys a constant frame rate bitstream to the decoder by encoding repeated frames as skip frames, or the encoder conveys a variable frame rate bitstream to the decoder by dropping repeated frames from the bitstream.

A display apparatus includes a display panel, a timing controller, a data driver and a voltage generator. The display panel includes a switching element, a pixel electrode connected to the switching element, a common electrode, a storage electrode and a pixel electrode. The timing controller processes input image data according to a variable frame rate and generates a data signal having a variable frame length. The data driver converts the data signal into a data voltage and outputs the data voltage to the pixel electrode. The voltage generator may apply a common voltage to the common electrode and a storage voltage greater than the common voltage to the storage electrode, and/or apply the common voltage varied according to a grayscale value of the input image data. Embodiments may reduce or obviate a display defect caused by luminance differences between frames displayed at different frame rates.

A method and apparatus for adjusting to a frame rate. The method displays the video frames with varying rates. The method comprising the steps of detecting a change in the frame rate, calculating the FREQ of the frame, adjusting the phase-locked loop utilizing the calculated FREQ, and utilizing the adjusted phase-locked loop output as the pixel clock to display the frame.

The invention discloses an ultra high speed ultrasonic imaging device and method based on a central processing unit (CPU) + a graphic processing unit (GPU) isomeric framework. An FPGA control probe transmits multi-angle plane wave ultrasonic signals to biological texture to be detected and conducts analog-to-digital conversion and pre-amplification on received data. A large amount of data subjected to preprocessing are transferred into a CPU through a high speed PCI e channel. Data beam forming is achieved in the CPU, and functions like human-computer interaction are achieved. GPU reads data in the inner storage of the CPU, and utilizes the parallel calculation capability and variable frame rate plane wave composite technology to combine and demodulate signals to further achieve super speed imaging. By means of the device and the method, the high-integrity transmitting and receiving scheme and the unified data collection framework are adopted to simplify the front end, the beam forming module is moved to the rear end, the front end is further simplified, the rear end processing capability is fully utilized, and the system performance is improved.

When signal-recording-and-reproducing portion 30 records an image signal DVb of a variable frame-rate picked-up image generated by a image signal generation portion 10 if it is instructed to reproduce the image signal, the recorded signal is reproduced and supplied to a frame rate conversion portion 21 as an image signal DVr. The frame rate conversion portion 21 converts the image signals DVb and DVr to a display frame rate and supplies them to a monitor image signal generation portion 41 as image signals DVb′ and DVr′. The monitor image signal generation portion 41 generates a monitor image displaying images based on the image signals DVb′ and DVr′ on a screen. Adjusting the frame rate referring to reproduced image displayed together with an image that is being shot allows an image signal to be easily generated so that a motion of a subject can be matched to a desired speed at the reproduction thereof.

The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate. The second video frame is then read from the second single-ported memory upon completing the writing of the second video frame in the second ported memory. The reading of the second video frame is then repeated from the second single-ported memory to maintain the second frame rate.

The invention relates to video processing and discloses an interlace compressed display method and an interlace compressed display system for reducing video frame rate. According to the invention, a field picture is selected every other X fields, wherein X is a positive even number, and video compressed encoding is performed only on the selected field picture, and thus, the field rate after field picture selection is 1/(X+1) that before field picture selection. In addition, an interlace display device can match a de-interlacing algorithm to recover one frame picture from one field picture, so that the resolution and the fluency of displayed videos can be improved effectively under the condition that code rate bandwidth is limited.

The invention discloses a method for converting video frame rate. Each frame in an input video sequence has a time stamp; and the video sequence is input in an ascending order according to the time stamp; and after a desired time stamp of each output frame is calculated, a frame closest to the desired time stamp is selected from an input frame queue and output. The method has the advantages of supporting the conversion from any input frame rate to any output frequency rate not greater than the input frequency rate, supporting the input of variable frame rate and having high tolerance, along with high universality and high stability.

The method of measuring video frame rate of video coding/decoding system includes the following steps: inputting the video sequence file with known size and video frame rate to the digital video coding/decoding system to be measured; outputting the video sequence file through processing in the digital video coding/decoding system and saving in one memory; calculating the video frame rate of the digital video coding/decoding system in formula F2=F1X(A2XA1), where, F2 is the video frame rate of the digital video coding/decoding system to be measured, F1 is the video frame rate of the known video sequence file, A1 is the size of the known video sequence file, and A2 is the size of video sequence file in the memory. The method of the present invention can measure video frame rate of video coding/decoding system without needing the tester's authority of operating the inner program inside video coding/decoding system, and is suitable for both white box system and black box system.

A method encodes a video as video objects. For each candidate object, a quantizer parameter and a skip parameter that jointly minimizes an average total distortion in the video are determined while satisfying predetermined constraints. The average total distortion includes spatial distortion of coded objects and spatial and temporal distortion of uncoded objects. Then, the candidate objects is encoded as the coded objects with the quantizer parameter and the skip parameter, and the candidate objects is skipped as the uncoded objects with the skip parameter.

The embodiment of the invention discloses an anchor end live video frame processing method, device, apparatus, system and medium. The method comprises the following steps: acquiring at least one livevideo frame acquired in real time at a variable frame rate in a live broadcast process; updating and storing the latest collected live video frame as a target live video frame in real time; and according to the target live broadcast video frame, pushing a live broadcast video stream with a set fixed frame rate or a set frame rate range to a live broadcast server, so that the live broadcast serversends the live broadcast video stream to a corresponding audience terminal for playing. According to the technical scheme, frame rate stability when the anchor terminal pushes the stream to the live broadcast server is ensured, and the problem that video playing is blocked or even a black screen occurs after the audience terminal pulls the stream is avoided.

A data conversion apparatus is provided with a temporary storage means for temporarily holding inputted variable-frame-rate coded data, a coded data time stamp reading means for reading a coded data time stamp of the inputted coded data, a time stamp conversion means for converting the coded data time stamp into an MP4 time stamp, and a fixed FPS means for converting the variable-frame-rate coded data into fixed-frame-rate coded data.