A control device, a multi-operator control method, a hardware scheduler, an accelerator, and a computing
system are disclosed. In this embodiment, multiple first cache allocation instructions are decoded by an instruction decoding circuit and then executed by an instruction execution circuit. Caches are allocated to multiple operators from a shared cache
pool, enabling data to be transferred between operators through the caches. This achieves soft connections and fast data interaction between operators. While ensuring
processing efficiency, the connection relationship between operators can be changed according to application needs, improving the application flexibility of hardware accelerators using multiple operators.