Germanium-painting structure for insulating layer of mixed graphical monocrystaline silicon as well as method and application thereof

Abstract

The invention relates to a germanium-on-insulator (GeOI) structure mixed with patterned single-crystal silicon and a manufacturing method thereof. The GeOI structure is characterized in that an active layer is composed of single-crystal germanium and single-crystal silicon, and the crystal orientation of the single-crystal silicon is determined by substrate silicon. The key point for preparing the structure is to prepare a GeOI single-crystal film. The substrate with the GeOI structure mixed with patterned single-crystal silicon is prepared by the steps of: transferring a single-crystal germanium film on an insulator by using plasma low temperature bonding and low temperature stripping techniques, and performing selective etching and single-crystal silicon epitaxy on the single-crystal germanium film. The inventive GeOI structure mixed with patterned single-crystal silicon can be used for gallium arsenide epitaxy, so as to integrate with III-V semiconductors. Meanwhile, the patterned single-crystal silicon material can be used for conventional CMOS processing to prepare conventional devices and circuits, so as to effectively solve the self healing effect of an embedded oxidation layer. The GeOI structure mixed with patterned single-crystal silicon has important application prospects in high-speed high-performance CMOS devices, optoelectronic integrated circuits, high-speed photodetectors, etc.

Description

technical field [0001] The invention relates to a germanium structure on an insulating layer of mixed patterned single crystal silicon and a manufacturing method thereof, belonging to the field of microelectronics. Background technique [0002] With the development of large-scale integrated circuit manufacturing technology, the feature size of its devices is also shrinking. Since 2006, the 65nm production lines of Intel Corporation, Texas Instruments, South Korea's Samsung, and Japan's Toshiba have successively entered the mass production stage, and 32nm and 22nm CMOS technologies are in the research and development stage. The development of integrated circuits has reached the current extremely large-scale era, and the existing bulk silicon materials and processes are approaching their physical limits. To further improve circuit speed and device performance, new breakthroughs must be made in materials and processes in order to achieve CMOS in the future. Moore's Law is main...

AI Technical Summary

Problems solved by technology

However, we also need to note that the content of germanium materials in the earth's crust is low, and it is more difficult to obtain high-quality single crystal germanium than silicon

Moreover, the band gap of Ge material is small (about 0.67eV at room temperature), which leads

Images