19 results about "Optoelectronic integrated circuits" patented technology

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a parallel PWM expansion high-precision programmable DAC structure. The adjusting module is used for adjusting the thermo-optical phase shifter according to the received digital control signal; the DAC structure specifically comprises a pulse width modulation signal generator and a current source array, wherein the pulse width modulation signal generator is used for acquiring a low-order code element from the digital control signal to generate a pulse width modulation signal, and sending the pulse width modulation signal to the current source array; wherein the current source array is used for acquiring a high-order code element from the digital control signal to generate a high-order analog signal; a low-order analog signal is generated based on the pulse width modulation signal; and the processor is also used for weighting and accumulating the low-order analog signal and the high-order analog signal to obtain an analog control signal and outputting the analog control signal. The DAC structure is high in precision and simple in structure.

This invention discloses a control method, system, and medium for a DC offset compensation circuit of an optical transceiver driver chip, relating to the field of optoelectronic integrated circuit testing technology. The method includes the following steps: time-aligning the test waveform and bias trajectory of the optical transceiver driver chip; extracting the phase misalignment and amplitude jump between beats; and mapping the continuous changes to a timing conflict observation band for identifying beat overlap regions. Based on the phase misalignment trend of the timing conflict observation band, the beat overlap points of the DC offset compensation loop are determined, and an overlap beat index is generated based on the duration and polarity of the amplitude jump to identify interfering nodes. This invention achieves millisecond-level beat observation and microsecond-level overlap identification during the testing phase, accurately extracting interfering nodes and constructing a coupling strength map. Combined with beat rearrangement and energy unloading strategies, it suppresses nonlinear oscillations, reduces oscillation and overload risks, improves eye diagram quality and bit error rate stability, and enhances the accuracy and robustness of chip testing.

The invention relates to a compound containing a cation represented by the following chemical formula 1, an electro-optical material, an electro-optical modulator, and an optoelectronic integrated circuit. [Chemical Formula 1] In Chemical Formula 1, A, D, L1, L2, R3a, and R3b are as defined in the specification.

The application relates to an active electromagnetic metasurface for realizing programmable topology polariton waveguide, which is composed of basic functional units combined with varactor diodes and periodically extended in a two-dimensional plane; the basic functional unit comprises two layers of dielectric, four layers of metal and a metallized via; by changing the applied bias voltage, reconfigurable topology transmission of magnetic polariton dispersion topology from ellipse to straight line and hyperbola can be realized; by means of wavefront characteristics under different dispersion topologies, adjustable field channeling and reconfigurable flat panel focusing functions and programmable topology polariton waveguide design can be realized. The application supports flexible propagation and guiding manipulation of surface waves, has the advantages of low dimension, real-time response, continuous controllability and high stability, provides an effective platform for active optoelectronic integrated circuit research, is beneficial to the design of planar integrated high-speed communication components, high-resolution imaging and high-sensitivity sensing and positioning systems, and has wide application prospects in the fields of near-field information processing and energy collection.

The invention provides an integrated driving chip for rapid wavelength tuning of a semiconductor laser array and a driving method of the integrated driving chip, and relates to the field of semiconductor optoelectronic integrated circuits. The driving chip comprises a packaging body, and the packaging body comprises a VCC pin, a VSS pin, an SW pin, a DACin pin and an Iout pin, wherein the SW pin, the DACin pin and the Iout pin are respectively provided with eight paths of driving currents. The packaging body comprises a current size setting module which uses a DACin pin to input a level so as to set a laser driving current; the high-speed switch switching module is used for switching laser channels by using an SW pin; and the multi-stage current mirror amplification module is used for converting and amplifying the final driving current by utilizing a preceding-stage level, and outputting the final driving current by an Iout pin. The tunable laser has important significance in improving the tuning range of the tunable laser, increasing the number of channels, shortening the channel switching time and reducing the size and the cost of the tunable laser.

Embodiments described herein relate to electronic and photonic integrated circuits and methods for fabricating integrated interconnect between electrical, opto-electrical and photonic devices. One or more optical silicon photonic devices described herein may be used in connection with one or more opto-electrical integrated circuits (opto-electrical chip) on a single package substrate to from a co-packaged optical and electrical device. The methods described herein enable high volume manufacturing of electrical, opto-electrical and the optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integral with a photonic glass layer substrate.

An optical-electrical integrated device includes a wiring board having a first insulating layer that includes a resin as a main component, and an interconnect layer disposed on the first insulating layer and including a pad, a photonic integrated circuit disposed on the first insulating layer and electrically connected to the pad, an optical fiber disposed on the first insulating layer and configured to transmit and receive an optical signal to and from the photonic integrated circuit, and a fixing member made of glass, disposed on the first insulating layer, and configured to clamp the optical fiber between the first insulating layer and the fixing member.

An optical-electrical integrated device includes a wiring board having a glass layer, and an interconnect layer disposed on the glass layer and including a pad, a photonic integrated circuit disposed on the glass layer and electrically connected to the pad, an optical fiber disposed on the glass layer and configured to transmit and receive an optical signal to and from the photonic integrated circuit, and a fixing member made of glass, disposed on the glass layer, and configured to clamp the optical fiber between the glass layer and the fixing member.

Multilayer packaging arrangements of photonic integrated circuit dies (PIC dies), as well as associated devices, systems, and manufacturing processes, are disclosed. A packaging arrangement comprises a lower layer with a base PIC die that provides at least part of the functionality of a PIC core or PIC unit. A photonic coupler is located in an upper layer of the packaging arrangement and optically couples the arrangement to external optical components. At least one middle layer of the packaging arrangement, between the base PIC die and the photonic coupler, comprises PIC dies, electronic integrated circuit dies (EIC dies), or hybrid photonic electronic IC dies (hybrid IC dies), or combinations thereof. The dies of the middle layer can provide the remaining functionality of the PIC core or PIC unit.A photonic via extends vertically through the middle layer and optically couples the PIC die and the photonic coupler.

includes a first wiring board, a plurality of second wiring boards, each second wiring board of the plurality of second wiring board being equipped with an integrated circuit, and an optical waveguide board. The plurality of second wiring boards and the optical waveguide board are disposed at different positions on an upper surface of the first wiring board in a plan view, and each second wiring board is optically connected to optical waveguide board.

This invention relates to the fields of electromagnetic shielding and micro / nano photonics, and discloses a near-field shield based on layered hyperbolic metamaterials and its fabrication method. The shield is constructed by stacking a substrate, a layered hyperbolic metamaterial, and a capping layer sequentially from bottom to top. The layered hyperbolic metamaterial is composed of alternating metal and dielectric layers, with each functional layer having a subwavelength thickness. The capping layer is located on the outermost side to provide impedance matching and physical protection. In this subwavelength layered structure, utilizing its unique hyperbolic dispersion characteristics in the operating wavelength band, external near-field evanescent waves can be efficiently coupled into volume modes within the structure, and absorbed and dissipated through the ohmic loss of the metal layers, thereby blocking electromagnetic energy penetration towards the substrate. This invention features a compact structure and process compatibility, effectively solving the problem of near-field signal crosstalk between adjacent components in high-density optoelectronic integrated circuits, and has significant application value in the electromagnetic compatibility design of on-chip optical interconnects and nanophotonic devices.

Integrated circuitry is fabricated from semiconductor layers that include a p-type gate-all-around (GAA) layer structure with quantum well structures formed between a pair of p-type thin doped layers. A p-type layer is formed above the p-type GAA layer structure. P-type ions are implanted into exposed parts of the p-type layer to extend through the p-type GAA layer structure and contact the p-type thin doped layers of the p-type GAA layer structure. A gate electrode of an n-channel HFET device is formed in contact with the ion-implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with ion-implanted n-type regions that contact the plurality of quantum well structures of the p-type GAA layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and other circuits, and optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a micro-ring heat regulator with a square root compression characteristic. The micro-ring heat regulator comprises a digital-to-analog conversion module, a square root compression module, a driving module and a heating module, the digital-to-analog conversion module is used for converting the received digital control signal into an analog control signal and outputting the analog control signal to the square root compression module; the square root compression module is used for solving the square root of the analog control signal and outputting the square root as a square root signal to the driving module; the driving module is used for carrying out power amplification based on the square root signal and driving the heating module to raise the temperature; the heating module is used for heating the micro-ring waveguide. The heating power output by the micro-ring thermal regulator and the input control signal present a highly linear relationship, and an ideal linear control basis is provided for thermal tuning of the micro-ring waveguide.

The invention provides a thin film lithium niobate electro-optical modulator with a segmented electrode structure, which belongs to the field of photoelectric integrated devices and is composed of a lithium niobate substrate, a silicon dioxide buffer layer, a thin film waveguide layer and a segmented electrode layer from bottom to top. Impedance matching is optimized, loss is reduced, and high-speed data transmission under low energy consumption is achieved. Through the segmented electrode design, the bandwidth and efficiency of the modulator are improved, stray capacitance and resistance are reduced, and electric field distribution is optimized. The device has remarkable advantages in the fields of high-speed optical communication, photoelectric integrated circuits and the like, and has huge application potential in the emerging fields of quantum communication and the like. The preparation process relates to a plurality of processes, such as SMART CUT, buffer proton exchange, photoetching and the like, so that the performance and the stability of the device are ensured.

Disclosed are a compound, an electro-optic material, an electro-optic modulator, an optoelectronic integrated circuit, an optical communication device, and a method of manufacturing an electro-optic modulator, the compound comprising a cation represented by Chemical Formula 1. In Chemical Formula 1, A, D, L 1 , L 2 , R 3a , and R 3b are the same as described in the detailed description.

An optical-electrical integrated device includes a first board, a second board facing a first region of the first board and coupled to the first board via a connecting member disposed in the first region, a semiconductor device mounted on the first or second board, an encapsulating resin filled between the first region and the second board to cover the connecting member and the semiconductor device, a PIC mounted on a side of the second board opposite from the first board and coupled to the semiconductor device, an optical component disposed adjacent to the PIC on a second region of the first board not facing the second board and enabling transmission and reception of optical signals to and from the PIC, and a bonding material disposed between each of the PIC and the encapsulating resin and the optical component to bond the PIC, the optical component, and the encapsulating resin together.

A semiconductor package includes a first semiconductor chip including first chip pads on a lower surface of the first semiconductor chip, a photonics chip including a photonic integrated circuit and second chip pads on an upper surface of the photonics chip, and first conductive pillars interposed between the first chip pads and the second chip pads.

The invention discloses a silicon photon CIS sensor heterogeneous integration packaging structure and method. The method comprises the steps that 1) a photon engine is prepared, an optical / electric integrated circuit is integrated and vertically connected through a copper needle, and a lens coupler is arranged at the optical input end; (2) a CIS chip is inversely arranged on the first RDL layer through a micro-bump, a photosensitive area is hollowed out, a vertical interconnection channel embedded with a first copper column is formed by adopting a TIV technology, a CIS packaging layer is coated with a light-transmitting material, and an optical micro-mirror is integrated on one side of the CIS packaging layer; (3) preparing an ASIC chip; 4) preparing an intermediate layer, and forming a second copper column, an upper bonding pad and a lower bonding pad by adopting a TSV process; according to the invention, TIV, copper column interconnection and CPO heterogeneous integration are combined, the reliability problem of a traditional TSV is overcome, high-bandwidth, low-power-consumption, miniaturized and high-performance packaging is realized, and the packaging structure is suitable for high-speed sensing and data transmission scenes.