48 results about "Optoelectronic integrated circuits" patented technology

Embodiments described herein also relate to electronic and photonic integrated circuits, and methods for fabricating integrated interconnects between electrical, optoelectronic and photonic elements. One or more optical silicon photonic elements described herein may be used on a single package substrate in conjunction with one or more optoelectronic integrated circuits (optoelectronic chips) to form co-packaged optical and electrical elements. The methods described herein enable mass fabrication of electrical, optoelectronic, and optical silicon photonic elements having a plurality of optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

The invention relates to an active electromagnetic metasurface for realizing a programmable topological polariton waveguide. The metasurface is formed by periodically extending basic function units and variable capacitance diodes in a two-dimensional plane; the basic function unit comprises two layers of media, four layers of metal and metalized via holes; by changing the applied bias voltage, reconfigurable topology transmission of the magnetic polarization excimer dispersion topology from an ellipse to a straight line and a hyperbolic curve can be realized; by means of wavefront characteristics under different dispersion topologies, adjustable field channelization and reconfigurable plate focusing functions and programmable topology polariton waveguide design can be realized. The device supports flexible propagation and guide control of surface waves, has the advantages of low dimensionality, real-time response, continuous controllability and high stability, provides an effective platform for active optoelectronic integrated circuit research, facilitates design of a plane integrated high-speed communication assembly, high-resolution imaging and a high-sensitivity sensing positioning system, and has wide application prospects. The method has wide application prospects in the fields of near-field information processing, energy collection and the like.

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a parallel PWM expansion high-precision programmable DAC structure. The adjusting module is used for adjusting the thermo-optical phase shifter according to the received digital control signal; the DAC structure specifically comprises a pulse width modulation signal generator and a current source array, wherein the pulse width modulation signal generator is used for acquiring a low-order code element from the digital control signal to generate a pulse width modulation signal, and sending the pulse width modulation signal to the current source array; wherein the current source array is used for acquiring a high-order code element from the digital control signal to generate a high-order analog signal; a low-order analog signal is generated based on the pulse width modulation signal; and the processor is also used for weighting and accumulating the low-order analog signal and the high-order analog signal to obtain an analog control signal and outputting the analog control signal. The DAC structure is high in precision and simple in structure.

The invention relates to the technical field of glass, and particularly discloses low dielectric loss glass and a preparation method thereof, the low dielectric loss glass comprises the following components by weight: 65%-70% of SiO2, 6%-11% of B2O3, 10%-15% of CaF2 + MgF2, 5%-10% of Al2O3, 1%-3% of ZrO2, 1%-3% of Na2O, 1%-10% of RE2O3 and 0.1%-2% of Li2O. The low-dielectric-loss glass provided by the invention shows excellent electrical performance in high-frequency application, can effectively reduce signal loss, and is suitable for microwave communication equipment, a high-frequency circuit substrate, a radio frequency device (such as an antenna and a filter), a photoelectric integrated circuit and other application scenes requiring low dielectric constant and low dielectric loss under a high-frequency condition; the invention provides a new choice for research and development of high-performance electronic devices, and has a wide application prospect.

This invention discloses a control method, system, and medium for a DC offset compensation circuit of an optical transceiver driver chip, relating to the field of optoelectronic integrated circuit testing technology. The method includes the following steps: time-aligning the test waveform and bias trajectory of the optical transceiver driver chip; extracting the phase misalignment and amplitude jump between beats; and mapping the continuous changes to a timing conflict observation band for identifying beat overlap regions. Based on the phase misalignment trend of the timing conflict observation band, the beat overlap points of the DC offset compensation loop are determined, and an overlap beat index is generated based on the duration and polarity of the amplitude jump to identify interfering nodes. This invention achieves millisecond-level beat observation and microsecond-level overlap identification during the testing phase, accurately extracting interfering nodes and constructing a coupling strength map. Combined with beat rearrangement and energy unloading strategies, it suppresses nonlinear oscillations, reduces oscillation and overload risks, improves eye diagram quality and bit error rate stability, and enhances the accuracy and robustness of chip testing.

The application discloses an optical connector assembly, which comprises a first transmission assembly, a second transmission assembly and an optical amplifier device. The first transmission assembly comprises a first optical cable unit, a first connecting module arranged at one end of the first optical cable unit and used for connecting with an optical / electrical integrated circuit, and a second connecting module arranged at the other end of the first optical cable unit. The second transmission assembly comprises a second optical cable unit, a third connecting module arranged at one end of the second optical cable unit, and a cable end connector arranged at the other end of the second optical cable unit and used for connecting with an application device. The optical amplifier device comprises a first end part optically aligned with the first optical cable unit and a second end part optically aligned with the second optical cable unit, so that the optical signal transmission quality is improved.

The invention relates to a compound containing a cation represented by the following chemical formula 1, an electro-optical material, an electro-optical modulator, and an optoelectronic integrated circuit. [Chemical Formula 1] In Chemical Formula 1, A, D, L1, L2, R3a, and R3b are as defined in the specification.

The application relates to an active electromagnetic metasurface for realizing programmable topology polariton waveguide, which is composed of basic functional units combined with varactor diodes and periodically extended in a two-dimensional plane; the basic functional unit comprises two layers of dielectric, four layers of metal and a metallized via; by changing the applied bias voltage, reconfigurable topology transmission of magnetic polariton dispersion topology from ellipse to straight line and hyperbola can be realized; by means of wavefront characteristics under different dispersion topologies, adjustable field channeling and reconfigurable flat panel focusing functions and programmable topology polariton waveguide design can be realized. The application supports flexible propagation and guiding manipulation of surface waves, has the advantages of low dimension, real-time response, continuous controllability and high stability, provides an effective platform for active optoelectronic integrated circuit research, is beneficial to the design of planar integrated high-speed communication components, high-resolution imaging and high-sensitivity sensing and positioning systems, and has wide application prospects in the fields of near-field information processing and energy collection.

The invention provides an integrated driving chip for rapid wavelength tuning of a semiconductor laser array and a driving method of the integrated driving chip, and relates to the field of semiconductor optoelectronic integrated circuits. The driving chip comprises a packaging body, and the packaging body comprises a VCC pin, a VSS pin, an SW pin, a DACin pin and an Iout pin, wherein the SW pin, the DACin pin and the Iout pin are respectively provided with eight paths of driving currents. The packaging body comprises a current size setting module which uses a DACin pin to input a level so as to set a laser driving current; the high-speed switch switching module is used for switching laser channels by using an SW pin; and the multi-stage current mirror amplification module is used for converting and amplifying the final driving current by utilizing a preceding-stage level, and outputting the final driving current by an Iout pin. The tunable laser has important significance in improving the tuning range of the tunable laser, increasing the number of channels, shortening the channel switching time and reducing the size and the cost of the tunable laser.

The invention discloses a photoelectric integrated circuit overload protection device, which belongs to the technical field of photoelectric integrated circuits, and comprises a circuit monitoring module used for acquiring real-time data of a photoelectric integrated circuit; the data processing module is used for processing real-time data of the photoelectric integrated circuit; the evaluation and analysis module is used for evaluating and analyzing the characteristic data of the photoelectric integrated circuit and determining an overload evaluation and analysis result of the photoelectric integrated circuit; and the overload protection module is used for performing intelligent overload protection on the photoelectric integrated circuit. The problems that the overload behavior of the photoelectric integrated circuit cannot be monitored and identified in real time and effective overload protection cannot be carried out on the photoelectric integrated circuit in the prior art, so that the reliability and the safety of the operation of the photoelectric integrated circuit are low are solved. According to the invention, the overload behavior of the photoelectric integrated circuit can be monitored and identified in real time, effective overload protection can be carried out on the photoelectric integrated circuit, and the operation reliability and safety of the photoelectric integrated circuit can be improved.

The embodiments described herein also relate to methods for fabricating electronic and photonic integrated circuits, and integrated interconnects between electrical, optoelectronic, and photonic devices. One or more optical silicon photonic devices described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single package substrate to form co-packaged optical and electrical devices. The methods described herein enable the mass production of electrical, optoelectronic, and optical silicon photonic devices with multiple optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

The invention discloses a testing device for an optoelectronic integrated circuit before co-packaging. The testing device comprises a first jig, a first optical transmission assembly, a second optical transmission assembly, an intermediate plate, a testing carrier plate and a second jig, the first jig and the second jig are arranged up and down in the direction perpendicular to the test carrier plate. The first photonic crystal grain and the second electronic integrated circuit are arranged in the accommodating space of the first jig. The first electronic integrated circuit is arranged in the groove part of the second jig. A first signal transmission loop is formed among the test carrier plate, the first electronic integrated circuit, the first photon crystal grain and the second photon crystal grain, and a second signal transmission loop is formed among the test carrier plate, the first electronic integrated circuit, the intermediate plate and the second electronic integrated circuit. Therefore, the problem that the photoelectric integrated circuit must be disassembled or taken back when defects are found in a test after co-packaging is avoided.

The present invention belongs to the technical field of optoelectronic integrated circuits, and particularly relates to a GeSn light-emitting diode with a magnetostrictive strain source and a preparation method thereof. The light-emitting diode includes a substrate layer, a relaxation layer, and an active region arranged in sequence from bottom to top. The active region includes an n+ type layer, an intrinsic layer, and a p+ type layer arranged in sequence from bottom to top; the materials of the relaxation layer and the active region are both GeSn; the active region is a hollow structure, and a strain source is arranged in the active region. The bottom of the strain source extends to the relaxation layer, and the contact between the strain source and the active region and the relaxation layer is isolated by an insulating layer around and at the bottom of the strain source. The strain source can also extend to the bottom of the relaxation layer, and the insulating layer outside the strain source separates it from the active region, the relaxation layer, and the substrate layer. The strain source is composed of a giant magnetostrictive material. A first metal electrode is arranged on the top of the active region. A second metal electrode is arranged on the relaxation layer. The present invention can introduce a large tensile strain into the active region through the strain source, and finally improve the light emission efficiency of the strained GeSn light-emitting diode.

A test device for an optoelectronic integrated circuit before being co-packaged includes a first jig, a first optical transmission assembly, a second optical transmission assembly, an interposer, a test load board, and a second jig. The first jig and the second jig are arranged up and down in a direction perpendicular to the test load board. A first photonic die and a second electronic integrated circuit are arranged in an accommodation space of the first jig. A first electronic integrated circuit is disposed in a groove portion of the second jig. A first signal transmission loop is formed between the test load board, the first electronic integrated circuit, the first photonic die, and the second photonic die. A second signal transmission loop is formed between the test load board, the first electronic integrated circuit, the interposer, and the second electronic integrated circuit.

Embodiments described herein relate to electronic and photonic integrated circuits and methods for fabricating integrated interconnect between electrical, opto-electrical and photonic devices. One or more optical silicon photonic devices described herein may be used in connection with one or more opto-electrical integrated circuits (opto-electrical chip) on a single package substrate to from a co-packaged optical and electrical device. The methods described herein enable high volume manufacturing of electrical, opto-electrical and the optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integral with a photonic glass layer substrate.

An optoelectronic integrated circuit testing device, configured to test optoelectronic integrated circuits, includes an automated testing equipment; an optical fiber connected to the automated testing equipment respectively; a receiving interface module disposed on the automated testing equipment, wherein the receiving interface module is provided with the optical fiber through hole for the optical fiber to pass through; a plurality of probes, wherein each probe is connected to the receiving interface module; and a guide plate module disposed on the receiving interface module, wherein the plurality of probes and the optical fiber pass through the guide plate module. The plurality of probes pressed against the optoelectronic integrated circuit when testing the optoelectronic integrated circuit, and the optical fiber receives optical communication signals transmitted from the optoelectronic integrated circuit.

An optical-electrical integrated device includes a wiring board having a first insulating layer that includes a resin as a main component, and an interconnect layer disposed on the first insulating layer and including a pad, a photonic integrated circuit disposed on the first insulating layer and electrically connected to the pad, an optical fiber disposed on the first insulating layer and configured to transmit and receive an optical signal to and from the photonic integrated circuit, and a fixing member made of glass, disposed on the first insulating layer, and configured to clamp the optical fiber between the first insulating layer and the fixing member.

A packaging structure for optoelectronic integrated circuits and a method for preparing the same are provided. By utilizing redistribution layers, one or more metal supports, a three-dimensional optical fiber wiring structure, a packaging layer, one or more optical chips, an electrical chip, metal bumps, a substrate, and one or more optical connectors, it enables the co-packaging of the optical chips and the electrical chip, thereby achieving stacked interconnection and staggered routing of the electrical signal wiring and the optical signal wiring. This technique reduces the packaging area, increases the wiring density, effectively shortens the transmission paths of optical and electrical signals, and reduces signal attenuation.Additionally, the optical fiber is extended from the sides of the package, improving modular integration capabilities, enabling system packaging, and meeting the requirements for high-density integrated packaging.

Embodiments described herein also relate to electronic and photonic integrated circuits and methods for fabricating integrated interconnect between electrical, opto-electrical and photonic devices. One or more optical silicon photonic devices described herein may be used in connection with one or more opto-electrical integrated circuits (opto-electrical chip) on a single package substrate to from a co-packaged optical and electrical device. The methods described herein enable high volume manufacturing of electrical, opto-electrical and the optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integral with a photonic glass layer substrate.

Embodiments described herein relate to methods for fabricating electronic and photonic integrated circuits and integrated interconnections between electrical, optoelectronic, and photonic devices. One or more optical silicon photonic devices described herein can be used in combination with one or more optoelectronic integrated circuits (optoelectronic chips) on a single packaging substrate to form co-packaged optoelectronic devices. The methods described herein enable the mass production of electrical, optoelectronic, and optical silicon photonic devices with multiple optical structures, such as waveguides, formed on or integrated with a photonic glass layer substrate.

An optical-electrical integrated device includes a wiring board having a glass layer, and an interconnect layer disposed on the glass layer and including a pad, a photonic integrated circuit disposed on the glass layer and electrically connected to the pad, an optical fiber disposed on the glass layer and configured to transmit and receive an optical signal to and from the photonic integrated circuit, and a fixing member made of glass, disposed on the glass layer, and configured to clamp the optical fiber between the glass layer and the fixing member.

Multilayer packaging arrangements of photonic integrated circuit dies (PIC dies), as well as associated devices, systems, and manufacturing processes, are disclosed. A packaging arrangement comprises a lower layer with a base PIC die that provides at least part of the functionality of a PIC core or PIC unit. A photonic coupler is located in an upper layer of the packaging arrangement and optically couples the arrangement to external optical components. At least one middle layer of the packaging arrangement, between the base PIC die and the photonic coupler, comprises PIC dies, electronic integrated circuit dies (EIC dies), or hybrid photonic electronic IC dies (hybrid IC dies), or combinations thereof. The dies of the middle layer can provide the remaining functionality of the PIC core or PIC unit.A photonic via extends vertically through the middle layer and optically couples the PIC die and the photonic coupler.

includes a first wiring board, a plurality of second wiring boards, each second wiring board of the plurality of second wiring board being equipped with an integrated circuit, and an optical waveguide board. The plurality of second wiring boards and the optical waveguide board are disposed at different positions on an upper surface of the first wiring board in a plan view, and each second wiring board is optically connected to optical waveguide board.

This invention relates to the fields of electromagnetic shielding and micro / nano photonics, and discloses a near-field shield based on layered hyperbolic metamaterials and its fabrication method. The shield is constructed by stacking a substrate, a layered hyperbolic metamaterial, and a capping layer sequentially from bottom to top. The layered hyperbolic metamaterial is composed of alternating metal and dielectric layers, with each functional layer having a subwavelength thickness. The capping layer is located on the outermost side to provide impedance matching and physical protection. In this subwavelength layered structure, utilizing its unique hyperbolic dispersion characteristics in the operating wavelength band, external near-field evanescent waves can be efficiently coupled into volume modes within the structure, and absorbed and dissipated through the ohmic loss of the metal layers, thereby blocking electromagnetic energy penetration towards the substrate. This invention features a compact structure and process compatibility, effectively solving the problem of near-field signal crosstalk between adjacent components in high-density optoelectronic integrated circuits, and has significant application value in the electromagnetic compatibility design of on-chip optical interconnects and nanophotonic devices.

To separate a process of forming a layer having electrical wiring and a process of forming a layer having optical wiring.SOLUTION: An optoelectronic integrated circuit 10 includes: a photonic integrated circuit 200 (PIC200); an interposer 300 having an electrical redistribution layer 310 (ERDL310) electrically connected to the PIC200; and a polymer waveguide layer 500 having an optical redistribution layer 510 (ORDL510) optically coupled to the PIC200. The interposer 300 and the polymer waveguide layer 500 are separate bodies.SELECTED DRAWING: Figure 3

Integrated circuitry is fabricated from semiconductor layers that include a p-type gate-all-around (GAA) layer structure with quantum well structures formed between a pair of p-type thin doped layers. A p-type layer is formed above the p-type GAA layer structure. P-type ions are implanted into exposed parts of the p-type layer to extend through the p-type GAA layer structure and contact the p-type thin doped layers of the p-type GAA layer structure. A gate electrode of an n-channel HFET device is formed in contact with the ion-implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with ion-implanted n-type regions that contact the plurality of quantum well structures of the p-type GAA layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and other circuits, and optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a micro-ring heat regulator with a square root compression characteristic. The micro-ring heat regulator comprises a digital-to-analog conversion module, a square root compression module, a driving module and a heating module, the digital-to-analog conversion module is used for converting the received digital control signal into an analog control signal and outputting the analog control signal to the square root compression module; the square root compression module is used for solving the square root of the analog control signal and outputting the square root as a square root signal to the driving module; the driving module is used for carrying out power amplification based on the square root signal and driving the heating module to raise the temperature; the heating module is used for heating the micro-ring waveguide. The heating power output by the micro-ring thermal regulator and the input control signal present a highly linear relationship, and an ideal linear control basis is provided for thermal tuning of the micro-ring waveguide.

This optical integrated circuit comprises a demultiplexer, a plurality of isolators, and a multiplexer. The demultiplexer divides input light into a plurality of different wavelength bands. The plurality of isolators have isolation functions respectively corresponding to the plurality of wavelength bands. The multiplexer is connected to the outputs of the plurality of isolators.

An optical interconnect may include an optoelectronic IC mounted to a substrate. The optoelectronic IC may have optoelectronic devices, for example microLEDs and / or photodetectors, mounted to a surface of the optoelectronic IC away from the substrate. The optoelectronic IC may have circuitry for driving the microLEDs and / or processing electrical signals from the photodetectors. The optoelectronic IC may be interfaced to a D2D interface chip. The D2D interface chip may be mounted to the optoelectronic IC.