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Fabrication method of multilayer graphene vertical interconnect structure

A multi-layer graphene, vertical interconnect technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high-frequency electrical performance impact, reduce overall electrical performance, etc., to improve electrical signal transmission performance. Effect

Inactive Publication Date: 2015-07-29
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this way, although the interconnection in the horizontal direction has very high conductivity, the vertical interconnection with relatively low conductivity still reduces the overall electrical performance, and signal reflections will occur at the connection between the horizontal graphene interconnection and the vertical metal interconnection, Great influence on high frequency electrical performance

Method used

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  • Fabrication method of multilayer graphene vertical interconnect structure
  • Fabrication method of multilayer graphene vertical interconnect structure
  • Fabrication method of multilayer graphene vertical interconnect structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0061] 1) First, if Figure 1a As shown, a substrate 110 is provided, and via holes 120 are formed. The substrate can be a semiconductor material, such as silicon, germanium and other simple semiconductors, or compound semiconductors such as gallium arsenide, indium phosphide, gallium nitride, etc.; it can also be a metal material, such as titanium, molybdenum, nickel, chromium, tungsten, copper, etc. Or its alloy; it can also be an insulating material such as glass or quartz. The substrate is generally circular, with notches or alignment edges made to distinguish or align crystal phases. Common substrate diameters are 50 mm, 100 mm, 200 mm, 300 mm, 450 mm, etc. Substrates can be standard thickness, ranging from 400 microns to 1000 microns, or thinned, ranging from 10 microns to 400 microns. The substrate 110 has a first substrate surface 111 and a second substrate surface 112, and the first substrate surface 111 and / or the second substrate surface 112 may have completed sem...

Embodiment 2

[0071] 1) According to step 1) to step 4) of embodiment 1, make through hole on substrate, and make insulating layer, catalyst layer and graphene successively. Next, if Figure 2a As shown, an insulating layer 220 is fabricated on graphene 410 . The insulating layer 220 can adopt dry oxygen thermal oxidation, wet oxygen thermal oxidation, hydrogen-oxygen synthesis thermal oxidation, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition. The material can be inorganic or organic, among which: inorganic substances such as silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, organic substances such as polyimide (PI), parylene (parylene) ), polybenzocyclobutene (BCB) or photoresist, or a mixture of the above materials or a composite insulating layer. The insulating layer 220 can be patterned, and the patterning can adopt methods such as reactive ion etching (RIE), deep reactive ion ...

Embodiment 3

[0078] 1) According to step 1) to step 6) of embodiment 1, make through holes on the substrate, and make insulating layer, catalytic layer, graphene, catalytic layer and graphene successively. Next, if Figure 3a As shown, an insulating layer 250 is fabricated on graphene 420 . The insulating layer 250 can adopt dry oxygen thermal oxidation, wet oxygen thermal oxidation, hydrogen-oxygen synthesis thermal oxidation, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition. The material can be inorganic or organic, among which: inorganic substances such as silicon oxide SiO2, silicon nitride Si3N4, aluminum oxide Al2O3, organic substances such as polyimide (PI), parylene (parylene) ), polybenzocyclobutene (BCB) or photoresist, or a mixture of the above materials or a composite insulating layer. The insulating layer 250 can be patterned, and the patterning can adopt methods such as reactive ion ...

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Abstract

The invention provides a manufacturing method of a multi-layer graphene vertical interconnected structure. The method comprises the following steps of: (S101) making a vertical hole on a substrate; (S102) making a catalyst layer on the surface of the substrate, wherein the catalyst layer covers the internal surface of the vertical hole; (S103) making a graphene layer on the catalyst layer; (S104) re-making the catalyst layer and the graphene layer until the desired conductive effect is obtained; and (S105) filling the vertical hole until the vertical hole is satisfactorily filled as required. By using the manufacturing method of the multi-layer graphene vertical interconnected structure, the electric signal transmission performance of the vertical interconnected structure can be improved.

Description

technical field [0001] The invention belongs to the technical field of manufacturing semiconductors and micro-sensors, and relates to a method for manufacturing a vertical interconnection structure between chips, in particular to a method for manufacturing a multilayer graphene vertical interconnection structure. Background technique [0002] The vertical interconnection between chips is a three-dimensional chip integration technology. Different from traditional packaging technology, it can provide electrical signal interconnection in the vertical direction, reduce interconnection parasitic parameters, improve system operating speed, and reduce system power consumption. The manufacturing method of the vertical interconnection structure between chips mainly includes processes such as making through holes on the chip, depositing an insulating layer in the through holes, and filling the through holes. The conductive material for filling the through hole is generally metal, suc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 朱韫晖方孺牛马盛林孙新陈兢缪旻金玉丰
Owner PEKING UNIV