Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper

Abstract

An aqueous removal composition having a pH in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W relative to low-k materials from a semiconductor substrate comprising said low-k materials having a TiN, TaN, TiNxOy, TiW, W, or alloy of Ti or W etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.

Description

CROSS REFERENCE TO RELATED APPLICATIONS / INCORPORATION BY REFERENCE STATEMENT[0001]This application claims the benefit of U.S. provisional application Ser. No. 61 / 889,968, filed Oct. 11, 2013, the entire contents of which are hereby incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]The presently disclosed and claimed inventive concept(s) relates to compositions and methods for selectively removing metal hardmask and other residues from integrated circuit (IC) device substrates, and, more particularly, to compositions and methods useful for selectively removing TiN, TaN, TiNxOy, TiW, and W metal hardmask, and metal hardmasks comprising alloys of the foregoing, as well as other residues from such substrates comprising low-k dielectric materials, TEOS, copper, cobalt and other low-k dielectric materials, using carboxylate compounds.[0003]Devices with critical dimensions on the order of 90 nanometers (nm) have involved integration of copper conductors and low-k dielectric...

AI Technical Summary

Benefits of technology

[0027]A composition formulated according to the invention and exhibiting an inherently high etch rate for TiN, TaN, TiNxOy, TiW and W, including alloys of Ti and W, enables processing at relatively low temperature, e.g., temperatures less than 65° C. A relatively low temperature process exhibits a reduced oxidizer decomposition rate, which, in turn, extends the useful composition bath life and pot life. Additionally, compositions according to the invention which exhibit high and selective etch rates for TiN, TaN, TiNxOy, TiW and W, including alloys of Ti and W, are desirable because they can reduce device processing time and thereby increase throughput. Typically, high etch rates for TiN, TaN, TiNxOy, TiW and W, including alloys of Ti and W, have been achieved by increasing process temperatures. However, for single wafer process applications, the highest processing temperature is around 75° C., which, in turn, can limit the upper end of etch rates for TiN, and thereby limit the ability for one to completely remove TiN metal hardmask from a dual damascene structure. Compositions according to the invention can effectively deliver high etch rates for TiN, TaN, TiNxOy, TiW and W, including alloys of Ti and W, with single wafer tool applications at a temperature range of from 20° C. to 60° C., and the TiN, TaN, TiNxOy, TiW and W, including alloys of Ti and W, metal hardmask can be fully removed with single wafer application process equipment if so desired.

Problems solved by technology

As the technology nodes advance to 45 nm and smaller, the decreasing size of the semiconductor devices makes achieving critical profile control of vias and trenches more challenging.

Fabrication of advanced generation devices that require copper conductors and low-k dielectric materials (typically carbon-doped silicon oxide (SiOCH), or porous low-k materials) give rise to the problem that both materials can react with and be damaged by various classes of prior art cleaners.

Low-k dielectrics, in particular, may be damaged in the cleaning process as evidenced by etching, changes in porosity / size, and ultimately changes in dielectric properties.

Some residues may be cleaned in a very short period of time, while some residues require much longer cleaning procedures.

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